A survey of FPGA optimization methods for data center energy efficiency
M Tibaldi, C Pilato - IEEE Transactions on Sustainable …, 2023 - ieeexplore.ieee.org
This article provides a survey of academic literature about field programmable gate array
(FPGA) and their utilization for energy efficiency acceleration in data centers. The goal is to …
(FPGA) and their utilization for energy efficiency acceleration in data centers. The goal is to …
Clock gating and clock enable for FPGA power reduction
JP Oliver, J Curto, D Bouvier, M Ramos… - 2012 VIII Southern …, 2012 - ieeexplore.ieee.org
This paper presents experimental measurements of power consumption using different
techniques to turn off part of a system and switch between active and standby modes. The …
techniques to turn off part of a system and switch between active and standby modes. The …
Low Power Techniques for Embedded FPGA Processors
The low-power techniques are essential part of VLSI design due to continuing increase in
clock frequency and complexity of chip. The synchronous circuit operates at highest clock …
clock frequency and complexity of chip. The synchronous circuit operates at highest clock …
A new reconfigurable clock-gating technique for low power SRAM-based FPGAs
Power consumption is dramatically increasing for Static Random Access Memory Field
Programmable Gate Arrays (SRAM-FPGAs), therefore lower power FPGA circuitry and new …
Programmable Gate Arrays (SRAM-FPGAs), therefore lower power FPGA circuitry and new …
Power-aware computing systems on FPGAs: a survey
A major concern with battery-operated devices is power-awareness and its appropriate
computing. The power dissipation of such systems is usually considered a hardware …
computing. The power dissipation of such systems is usually considered a hardware …
Multi-factorial energy aware resource management in edge networks
Edge networks deliver computing services close to the user, unlike centralized clouds. This
improves service scalability and delay-sensitive functions can be offloaded to the edge …
improves service scalability and delay-sensitive functions can be offloaded to the edge …
Clock gating methodologies and tools: a survey
G Pouiklis, GC Sirakoulis - International journal of Circuit theory …, 2016 - Wiley Online Library
Clock gating (CG) is a widely used design method for reducing the dynamic power
consumption in digital circuits. Although it is a mature technique, theoretical work and tools …
consumption in digital circuits. Although it is a mature technique, theoretical work and tools …
An Ensemble Learning Approach for In-Situ Monitoring of FPGA Dynamic Power
As field-programmable gate arrays (FPGAs) become prevalent in critical application
domains, their power consumption is of high concern. In this paper, we present and evaluate …
domains, their power consumption is of high concern. In this paper, we present and evaluate …
Heuristic and statistical power estimation model for FPGA based wireless systems
As the technology is advancing day by day, the need of high performance devices is also
increasing. High performance is achieved at the expense of high power dissipation …
increasing. High performance is achieved at the expense of high power dissipation …
Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems
Generation and exploration of approximate circuits and accelerators has been a prominent
research domain to achieve energy-efficiency and/or performance improvements. This …
research domain to achieve energy-efficiency and/or performance improvements. This …