[BOOK][B] Low-power high-level synthesis for nanoscale CMOS circuits
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits addresses the need for
analysis, characterization, estimation, and optimization of the various forms of power …
analysis, characterization, estimation, and optimization of the various forms of power …
Application-driven power efficient ALU design methodology for modern microprocessors
N Gong, J Wang, R Sridhar - International Symposium on …, 2013 - ieeexplore.ieee.org
In this paper, we propose an application-driven ALU design methodology to achieve high
level of power efficiency for modern microprocessors. We introduce a PN selection algorithm …
level of power efficiency for modern microprocessors. We introduce a PN selection algorithm …
A nature-inspired firefly algorithm based approach for nanoscale leakage optimal RTL structure
Optimization of leakage power is essential for nanoscale CMOS (nano-CMOS) technology
based integrated circuits for numerous reasons, including improving battery life of the …
based integrated circuits for numerous reasons, including improving battery life of the …
Modeling and reduction of gate leakage during behavioral synthesis of nanoCMOS circuits
For a nanoCMOS of sub-65mn technology, where the gate oxide (SiO/sub 2/) thickness is
very low, the gate leakage is one of the major components of power dissipation. In this …
very low, the gate leakage is one of the major components of power dissipation. In this …
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits
SP Mohanty, R Velagapudi… - Proceedings of the …, 2006 - ieeexplore.ieee.org
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major
component of the total power dissipation. This paper presents a simulated annealing based …
component of the total power dissipation. This paper presents a simulated annealing based …
Simultaneous scheduling and binding for low gate leakage nano-complementary metal-oxide-semiconductor data path circuit behavioural synthesis
The authors present two polynomial time-complexity heuristic algorithms for optimisation of
gate-oxide leakage (tunnelling current) during behavioural synthesis through simultaneous …
gate-oxide leakage (tunnelling current) during behavioural synthesis through simultaneous …
Simultaneous power fluctuation and average power minimization during nano-CMOS behavioral synthesis
The authors present minimization methodologies and an algorithm for simultaneous
scheduling, binding, and allocation for the reduction of total power and power fluctuation …
scheduling, binding, and allocation for the reduction of total power and power fluctuation …
User guided high level synthesis
I Augé, F Pétrot - High-Level Synthesis: from Algorithm to Digital Circuit, 2008 - Springer
Abstract The User Guided Synthesis approach targets the generation of coprocessor under
timing and resource constraints. Unlike other approaches that discover the architecture …
timing and resource constraints. Unlike other approaches that discover the architecture …
Variability-aware architecture level optimization techniques for robust nanoscale chip design
The design space for nanoscale CMOS circuits is vast, with multiple dimensions
corresponding to process variability, leakage, power, thermal, reliability, security, and yield …
corresponding to process variability, leakage, power, thermal, reliability, security, and yield …
Dual-k versus dual-T technique for gate leakage reduction: a comparative perspective
SP Mohanty, R Velagapudi… - … Symposium on Quality …, 2006 - ieeexplore.ieee.org
As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has
become a major component of total power dissipation. Use of dielectrics of higher …
become a major component of total power dissipation. Use of dielectrics of higher …