A 28-nm 75-fsrms Analog Fractional- Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle …
W Wu, CW Yao, K Godbole, R Ni… - IEEE Journal of Solid …, 2019 - ieeexplore.ieee.org
An analog fractional-sampling phase-locked loop (PLL) is presented. It achieves 75-fs rms
jitter, integrated from 10 kHz to 10 MHz, and a− 249.7-dB figure of merit (FoM) at the …
jitter, integrated from 10 kHz to 10 MHz, and a− 249.7-dB figure of merit (FoM) at the …
A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB
AT Narayanan, M Katsuragi, K Kimura… - IEEE Journal of Solid …, 2016 - ieeexplore.ieee.org
A fractional-N sub-sampling PLL architecture based on pipelined phase-interpolator and
Digital-to-Time-Converter (DTC) is presented in this paper. The combination of pipelined …
Digital-to-Time-Converter (DTC) is presented in this paper. The combination of pipelined …
A 20-GHz PLL with 20.9-fs random jitter
This article describes an integer-phase-locked loop (PLL) that incorporates a phase detector
sampling both the rising and falling edges of the reference clock. The circuit also uses a new …
sampling both the rising and falling edges of the reference clock. The circuit also uses a new …
Benchmark figure of merit extensions for low jitter phase locked loops inspired by new PLL architectures
W Bae - IEEE Access, 2022 - ieeexplore.ieee.org
A conventional figure-of-merit (FOM) for a phase-locked loop (PLL) has served as the most
powerful indicator to compare and to normalize performance of different PLL designs …
powerful indicator to compare and to normalize performance of different PLL designs …
A 3.5–6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH -TDC for Low In-Band Phase Noise
This paper proposes a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth
all-digital phaselocked loop (ADPLL) with a fine-resolution time-to-digital converter (TDC) …
all-digital phaselocked loop (ADPLL) with a fine-resolution time-to-digital converter (TDC) …
9.6 A 2.7-to-4.3 GHz, 0.16 psrms-jitter,− 246.8 dB-FOM, digital fractional-N sampling PLL in 28nm CMOS
High-performance phase-locked-loops (PLLs) are key building blocks for many modern ICs.
The sub-sampling PLL proposed in [1] uses a reference clock REF to sample a high …
The sub-sampling PLL proposed in [1] uses a reference clock REF to sample a high …
A Sub-mW Fractional- ADPLL With FOM of −246 dB for IoT Applications
This paper presents a sub-mW fractional-N all-digital phase-locked loop (ADPLL) with
scalable power consumption, which achieves an figure of merit (FOM) of-246 dB. The …
scalable power consumption, which achieves an figure of merit (FOM) of-246 dB. The …
An 802.11a/b/g/n Digital Fractional- PLL With Automatic TDC Linearity Calibration for Spur Cancellation
A fractional-N digital phase-locked loop (PLL) architecture with low fractional spur is
presented in this paper. A 2-D Vernier time-to-digital convertor (TDC) is implemented to …
presented in this paper. A 2-D Vernier time-to-digital convertor (TDC) is implemented to …
Reference oversampling PLL achieving− 256-dB FoM and− 78-dBc reference spur
This article presents a low jitter, low power, low reference spur LC oscillator-based reference
oversampling digital phase locked loop (OSPLL). The proposed reference oversampling …
oversampling digital phase locked loop (OSPLL). The proposed reference oversampling …
A Reconfigurable Vernier Time-to-Digital Converter With 2-D Spiral Comparator Array and Second-Order Linearization
This paper presents an 8-bit 1.25-ps resolution reconfigurable Vernier time-to-digital
converter (TDC) with a 2-D spiral comparator array and ΔΣ modulators for linearization. The …
converter (TDC) with a 2-D spiral comparator array and ΔΣ modulators for linearization. The …