Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are
well-suited for VLSI implementations. A novel framework is introduced, which allows the …

The power consumption of integrated circuits is one of the most problematic considerations
affecting the design of high-performance chips and portable devices. The study of power …

A methodology for energy–delay optimization of digital circuits is presented. This
methodology is applied to minimizing the delay of representative carry-lookahead adders …

In this paper, we motivate the concept of comparing very large scale integration adders
based on their energy-delay characteristics and present results of our estimation technique …

Energy-efficient design requires exploration of available algorithms, recurrence structures,
energy and wire tradeoffs, circuit design techniques, circuit sizing and system constraints. In …

This paper presents an efficient reverse converter for transforming the redundant binary (RB)
representation into two's complement form. The hierarchical expansion of the carry equation …

In this paper, we present a carry skip adder (CSKA) structure that has a higher speed yet
lower energy consumption compared with the conventional one. The speed enhancement is …

In this brief, a new architecture for high-fan-in CMOS comparator is proposed. The
architecture is based on a hierarchical two-stage comparator structure and a dynamic MUX …

Heterogeneous multicores are envisioned to be a promising design paradigm to combat
today's challenges of power, memory, and reliability walls that are impeding chip design …

In this paper, we present a full-static carry-skip adder designed to achieve low power
dissipation and high-performance operation. To reduce the adder's delay and power …