Nimble page management for tiered memory systems
Software-controlled heterogeneous memory systems have the potential to increase the
performance and cost efficiency of computing systems. However they can only deliver on …
performance and cost efficiency of computing systems. However they can only deliver on …
Softsku: Optimizing server architectures for microservice diversity@ scale
The variety and complexity of microservices in warehouse-scale data centers has grown
precipitously over the last few years to support a growing user base and an evolving product …
precipitously over the last few years to support a growing user base and an evolving product …
Mosaic: a GPU memory manager with application-transparent support for multiple page sizes
Contemporary discrete GPUs support rich memory management features such as virtual
memory and demand paging. These features simplify GPU programming by providing a …
memory and demand paging. These features simplify GPU programming by providing a …
Hawkeye: Efficient fine-grained os support for huge pages
Effective huge page management in operating systems is necessary for mitigation of
address translation overheads. However, this continues to remain a difficult area in OS …
address translation overheads. However, this continues to remain a difficult area in OS …
Prefetched address translation
With explosive growth in dataset sizes and increasing machine memory capacities, per-
application memory footprints are commonly reaching into hundreds of GBs. Such huge …
application memory footprints are commonly reaching into hundreds of GBs. Such huge …
Mask: Redesigning the gpu memory hierarchy to support multi-application concurrency
Graphics Processing Units (GPUs) exploit large amounts of threadlevel parallelism to
provide high instruction throughput and to efficiently hide long-latency stalls. The resulting …
provide high instruction throughput and to efficiently hide long-latency stalls. The resulting …
Every walk'sa hit: making page walks single-access cache hits
As memory capacity has outstripped TLB coverage, large data applications suffer from
frequent page table walks. We investigate two complementary techniques for addressing …
frequent page table walks. We investigate two complementary techniques for addressing …
Elastic cuckoo page tables: Rethinking virtual memory translation for parallelism
The unprecedented growth in the memory needs of emerging memory-intensive workloads
has made virtual memory translation a major performance bottleneck. To address this …
has made virtual memory translation a major performance bottleneck. To address this …
Hybrid tlb coalescing: Improving tlb translation coverage under diverse fragmented memory allocations
To mitigate excessive TLB misses in large memory applications, techniques such as large
pages, variable length segments, and HW coalescing, increase the coverage of limited …
pages, variable length segments, and HW coalescing, increase the coverage of limited …
Translation ranger: Operating system support for contiguity-aware tlbs
Virtual memory (VM) eases programming effort but can suffer from high address translation
overheads. Architects have traditionally coped by increasing Translation Lookaside Buffer …
overheads. Architects have traditionally coped by increasing Translation Lookaside Buffer …