Design margin reduction through completion detection in a 28-nm near-threshold DSP processor

R Uytterhoeven, W Dehaene - IEEE Journal of Solid-State …, 2021 - ieeexplore.ieee.org
This article presents a timing error detection and correction (EDaC) technique optimized for
near-/sub-threshold operation to recover energy lost in the conventional signoff margins …

Beyond eliminating timing margin: An efficient and reliable negative margin timing error detection for neural network accelerator without accuracy loss

Z Shen, W Shan, Y Du, Z Li… - IEEE Journal of Solid-State …, 2022 - ieeexplore.ieee.org
Resilient circuits with timing error detection and correction (EDAC) can eliminate the excess
timing margin but suffer from miss detection risk due to inactivation of the critical paths. We …

DSC-TRCP: Dynamically self-calibrating tunable replica critical paths based timing monitoring for variation resilient circuits

Y Du, J Qian, Z Shen, C Wu, W Shan… - IEEE Journal of Solid …, 2024 - ieeexplore.ieee.org
In situ timing monitoring of critical paths (CPs) can help eliminate the excess timing margin
but suffer from miss detection risk because the CPs might not be activated. However, indirect …

Negative Design Margin Realization through Deep Path Activity Detection Combined with Dynamic Voltage Scaling in a 55 nm Near-Threshold 32-Bit Microcontroller

RZ Yu, ZH Li, X Deng, ZL Liu - Sensors, 2023 - mdpi.com
This paper presents an innovative approach for predicting timing errors tailored to near-/sub-
threshold operations, addressing the energy-efficient requirements of digital circuits in …

Catena: A near-threshold, sub-0.4-mW, 16-core programmable spatial array accelerator for the ultralow-power mobile and embedded Internet of Things

JP Cerqueira, TJ Repetti, Y Pu… - IEEE Journal of Solid …, 2020 - ieeexplore.ieee.org
In this article, we present Catena, a near-threshold voltage 16-core programmable spatial
array accelerator supporting workloads for ultralow-power (ULP) mobile and embedded …

Integrating error correction and detection techniques in RISC-V processor microarchitecture for enhanced reliability

A Sreekumar, BS Shankar, BNK Reddy - Integration, 2025 - Elsevier
An essential consideration in processor design is ensuring reliability, particularly in
demanding environments such as outer space and nuclear plants. To mitigate the effects of …

Design of light-weight timing error detection and correction circuits for energy-efficient near-threshold voltage operation

X Fan, H Liu, H Li, S Lu, J Han - Electronics, 2022 - mdpi.com
Near-threshold voltage (NTV) operation has the potential to improve the energy efficiency of
digital integrated circuits. However, the use of a conservative timing guard band to avoid the …

An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator without Accuracy Loss in 28nm CMOS

Z Li, W Shan, C Wu, H Ge… - 2021 IEEE Asian Solid …, 2021 - ieeexplore.ieee.org
Energy-efficient neural network (NN) accelerators are essential for IoT and mobile
applications, where PVT variations become severe especially in near-threshold voltage …

ATEP: An Asynchronous Timing Error Prediction Circuit With Adaptive Voltage and Frequency Scaling

C Zhang, D **ong, X Zhang, Z Wang… - … Transactions on Very …, 2024 - ieeexplore.ieee.org
Timing error prediction circuits have demonstrated greater efficiency in reducing the worst
case timing margins of conventional circuits. However, prior works of timing error prediction …

Margin Elimination in a 55 nm Near-Threshold Microcontroller with Adaptive Prediction Capability and Voltage Scaling

R Yu, Z Li, X Deng, Z Wang, H Zhang, Z Liu - Electronics, 2024 - mdpi.com
This paper presents an innovative approach for error prediction (EP) tailored to near-
threshold operations, addressing the energy-efficient requirements of digital circuits in …