SA-DS: A Dataset for Large Language Model-Driven AI Accelerator Design Generation

D Vungarala, M Nazzal, M Morsali, C Zhang… - arxiv preprint arxiv …, 2024 - arxiv.org
In the ever-evolving landscape of Deep Neural Networks (DNN) hardware acceleration,
unlocking the true potential of systolic array accelerators has long been hindered by the …

Integration of a systolic array based hardware accelerator into a DNN operator auto-tuning framework

FN Peccia, O Bringmann - Proceedings of the 2023 Workshop on …, 2023 - dl.acm.org
The deployment of neural networks on heterogeneous SoCs coupled with custom
accelerators is a challenging task because of the lack of end-to-end software tools provided …

NNASIM: An Efficient Event-Driven Simulator for DNN Accelerators with Accurate Timing and Area Models

X Yi, J Yu, Z Wu, X **ong, D Xu, C Chen… - … on Circuits and …, 2022 - ieeexplore.ieee.org
In this paper, we propose NNASIM, an efficient timing and area accurate event-driven
simulator for custom DNN accelerators. NNASIM is a highly-modular and highly …

CGRA-RISC: Simulation Infrastructure for Coupling CGRA Accelerator to RISC-V Processor

AFR Ribeiro - 2024 - search.proquest.com
The downtrend of Koomey's law, which accounts for the doubling of performance per joule
every 1.5 years, coupled with an emergent demand for high-performance and multi-domain …