Alewife is a multiprocessor architecture that supports up to 512 processing nodes connected
over a scalable and cost-effective mesh network at a constant cost per node. The MIT …

This paper presents CMP Cooperative Caching, a unified framework to manage a CMP's
aggregate on-chip cache resources. Cooperative caching combines the strengths of private …

Prior work shows that Rowhammer attacks---which flip bits in DRAM via frequent activations
of the same row (s)---are viable. Adversaries typically mount these attacks via instruction …

Many future shared-memory multiprocessor servers will both target commercial workloads
and use highly-integrated" glueless" designs. Implementing low-latency cache coherence in …

Recent benchmark suite releases such as Parsec specifically utilise the tightly coupled
cores available in chip-multiprocessors to allow the use of newer, high performance, models …

This paper introduces dynamic self-invalidation (DSI), a new technique for reducing cache
coherence overhead in shared-memory multiprocessors. DSI eliminates invalidation …

Database applications such as online transaction processing (OLTP) and decision support
systems (DSS) constitute the largest and fastest-growing segment of the market for …

The memory consistency model for a shared-memory multiprocessor specifies the behavior
of memory with respect to read and write operations from multiple processors. As such, the …

Parallel programs exhibit a small number of distinct data-sharing patterns. A common data-
sharing pattern, migratory access, is characterized by exclusive read and write access by …

Abstract The C/? egion Library(CRL) is a new all-software distributed shared memory (DSM)
system. CRL requires no special compiler, hardware, or operating system support beyond …