Workload-aware opportunistic energy efficiency in multi-fpga platforms
The continuous growth of big data applications with high computational and scalability
demands has resulted in increasing popularity of cloud computing. Optimizing the …
demands has resulted in increasing popularity of cloud computing. Optimizing the …
[KSIĄŻKA][B] Fast and Energy Efficient Big Data Processing on FPGAs
S Salamat - 2021 - search.proquest.com
With the rapid development of the Internet of things (IoT), networks, software, and computing
platforms, the size of the generated data is dramatically increasing, bringing the dawn of the …
platforms, the size of the generated data is dramatically increasing, bringing the dawn of the …
TEPD: A Compound Timing Detection of Both Data-Transition and Path-Activation for Reliable In-Situ Timing Error Detection and Correction in 28nm CMOS
Conservative timing margins are reserved in digital IC to resist process, voltage, and
temperature (PVT) variations, causing large power waste. It can be mitigated or eliminated …
temperature (PVT) variations, causing large power waste. It can be mitigated or eliminated …
High-Performance ADC Design Using Fast Prediction Logic with Dynamic Clock Stretching Mechanism
NS Babu, S Satheeskumaran… - … Computing and Data …, 2023 - ieeexplore.ieee.org
In high-performance ADC designs, time-borrowing techniques are commonly utilized to
reduce timing errors. A new dynamic flip-flop conversion mechanism has been developed in …
reduce timing errors. A new dynamic flip-flop conversion mechanism has been developed in …
Design and Optimization of Timing Errors on Swap** of Threshold Voltage
B Saurab, AP Chavan - 2021 IEEE Mysore Sub Section …, 2021 - ieeexplore.ieee.org
In recent years, demand for high-performance and low-power designs is increasing, and
also the complexity of the design is increasing due to the continuous scaling of technology …
also the complexity of the design is increasing due to the continuous scaling of technology …
Static Timing Analysis of Multibit Flipflop based LFSR
AA Prabhu, N Shylashree… - 2022 6th …, 2022 - ieeexplore.ieee.org
In the emerging VLSI technologies the industries demand for low power, area and to avoid
timing violations in the digital circuits. The setup and hold timing turned out to be one of the …
timing violations in the digital circuits. The setup and hold timing turned out to be one of the …
Static Timing Analysis of Nonlinear-Feedback Shift Register
S Hithesh, S Yugasni, C Uttam… - 2024 8th …, 2024 - ieeexplore.ieee.org
An 8-bit Non-Linear Feedback Shift Register (NLFSR) is designed and implemented using
Verilog, with synthesis and timing analysis conducted on the Vivado platform. The NLFSR …
Verilog, with synthesis and timing analysis conducted on the Vivado platform. The NLFSR …
[PDF][PDF] Efficient Low-Power Timing-Error Control in Digital Integrated Circuits Using Timing Error-Tolerant Circuits and Time-Borrowing Techniques
SG Priyadharshini, V Kanagasubramanian… - ijatem.com
In modern digital systems, real-time operation of integrated circuits is of paramount
importance. Presently, a significant portion of energy consumption is attributed to the …
importance. Presently, a significant portion of energy consumption is attributed to the …
Integrated circuit having an in-situ circuit for detecting an impending circuit failure
AM Jarrar, DR Tipple, EC Onyema - US Patent 11,680,983, 2023 - Google Patents
2022-02-01 Assigned to NXP USA, INC. reassignment NXP USA, INC. ASSIGNMENT OF
ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JARRAR, ANIS …
ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JARRAR, ANIS …