This paper presents a comprehensive survey of existing techniques for interconnect
optimization during the VLSI physical design process, with emphasis on recent studies on …

With the rise of many-core chips that require substantial bandwidth from the network on chip
(NoC), integrated photonic links have been investigated as a promising alternative to …

Recent years have seen significant progress in improving both the efficiency and
effectiveness of time series classification. However, because the best solution is typically the …

This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI
practitioners and researchers in need of fluency in an" adjacent" field will find this an …

This paper concerns a method for digital circuit optimization based on formulating the
problem as a geometric program (GP) or generalized geometric program (GGP), which can …

Model order reduction (MOR) techniques reduce the complexity of VLSI designs, paving the
way to higher operating speeds and smaller feature sizes. This book presents a systematic …

At modern technology nodes, improving routability and reducing total wirelength are no
longer sufficient to close timing. Incremental timing-driven placement (TDP) seeks to resolve …

Interconnect has become the dominating factor in determining circuit performance and
reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends …

Noise analysis and avoidance is an increasingly critical step in deep submicron design.
Ever increasing requirements on performance have led to widespread use of dynamic logic …

For performance optimization tasks such as floorplanning, placement, buffer insertion, wire
sizing, and global routing, the Elmore resistance-capacitance (RC) delay metric remains …