Hardware and software enabled implementation of power profile management instructions in system on chip
R Kaushal, A Gangwar, VM Pusuluri… - US Patent 9,568,970, 2017 - Google Patents
Aspects of the present disclosure relate to a method and system for hybrid and/or distributed
implementation of generation and/or execution of power profile management instructions …
implementation of generation and/or execution of power profile management instructions …
Configurable router for a network on chip (NoC)
J Philip, S Kumar - US Patent 9,742,630, 2017 - Google Patents
Example implementations described herein are directed to a configurable building block,
such as a router, for implementation of a Network on Chip (NoC). The router is …
such as a router, for implementation of a Network on Chip (NoC). The router is …
Automatic NoC topology generation
S Kumar, A Patankar, E Norige - US Patent 9,054,977, 2015 - Google Patents
6,415,282 6,456,961 6,925,627 7,065,730 7,318,214 7,590,959 7,724,735 7,725,859
7,808.968 7,917,885 7,957,381 8,050,256 8,059,551 8,099,757 8,136,071 8,203,938 …
7,808.968 7,917,885 7,957,381 8,050,256 8,059,551 8,099,757 8,136,071 8,203,938 …
Systems and methods for facilitating low power on a network-on-chip
JA Bauman, J Rowlands, S Kumar - US Patent 10,452,124, 2019 - Google Patents
Aspects of the present disclosure are directed to a power specification and Network on Chip
(NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC …
(NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC …
System and method for visualization of NoC performance based on simulation output
Aspects of the present disclosure are directed to methods, systems, and non-transitory
computer readable mediums for selective visualization and performance characterization of …
computer readable mediums for selective visualization and performance characterization of …
Automatic buffer sizing for optimal network-on-chip design
S Kumar - US Patent 9,660,942, 2017 - Google Patents
The present disclosure relates to automatic sizing of NoC channel buffers of one or more
virtual channels to optimize NoC design, SoC design, and to meet defined performance …
virtual channels to optimize NoC design, SoC design, and to meet defined performance …
Automatic power domain and voltage domain assignment to system-on-chip agents and network-on-chip elements
The present disclosure relates system and method for automatic assignment of power
domain and voltage domain to one or more SoC and/or NoC elements based on one or a …
domain and voltage domain to one or more SoC and/or NoC elements based on one or a …
Supporting multicast in NoC interconnect
Example implementations are directed to more efficiently delivering a multicast message to
multiple destination components from a source component. Multicast environment is …
multiple destination components from a source component. Multicast environment is …
System-on-chip (SoC) optimization through transformation and generation of a network-on-chip (NoC) topology
The present disclosure is directed to system-on-chip (SoC) optimization through
transformation and generation of a network-on-chip (NoC) topology. The present disclosure …
transformation and generation of a network-on-chip (NoC) topology. The present disclosure …
System level simulation in Network on Chip architecture
S Kumar, A Patankar, E Norige - US Patent 10,496,770, 2019 - Google Patents
Abstract Systems and methods for performing multi-message transaction based
performance simulations of SoC IP cores within a Network on Chip (NoC) interconnect …
performance simulations of SoC IP cores within a Network on Chip (NoC) interconnect …