Applying neural networks to delay fault testing: Test point insertion and random circuit training
This article presents methods of increasing logic built-in self-test (LBIST) delay fault
coverage using artificial neural networks (ANNs) to selecting test point (TP) locations a …
coverage using artificial neural networks (ANNs) to selecting test point (TP) locations a …
Improved random pattern delay fault coverage using inversion test points
This article analyzes and rationalizes the capabilities of inversion-based test points (TPs)
when implemented in lieu of control-0/1 TPs. With upward scaling of transistor density, delay …
when implemented in lieu of control-0/1 TPs. With upward scaling of transistor density, delay …
Improved pseudo-random fault coverage through inversions: a study on test point architectures
This article analyzes and rationalizes the capabilities of inversion test points (TPs) when
implemented in lieu of traditional test point architectures. With scaling transistor density …
implemented in lieu of traditional test point architectures. With scaling transistor density …
DelayAVF: Calculating Architectural Vulnerability Factors for Delay Faults
Reliability is a key design consideration for modern microprocessors. A surge of reports from
major cloud vendors describing new silent data corruption (SDC) behaviours at scale …
major cloud vendors describing new silent data corruption (SDC) behaviours at scale …
New perspectives on core in-field path delay test
Path Delay fault test currently exploits DfT-based techniques, mainly relying on scan chains,
widely supported by commercial tools. However, functional testing may be a desirable …
widely supported by commercial tools. However, functional testing may be a desirable …
Self-test library generation for in-field test of path delay faults
New semiconductor technologies for advanced applications are more prone to defects and
imperfections related, among several different causes, to the manufacturing process, aging …
imperfections related, among several different causes, to the manufacturing process, aging …
Switch level time simulation of CMOS circuits with adaptive voltage and frequency scaling
Design and test validation of systems with adaptive voltage-and frequency scaling (AVFS)
requires timing simulation with accurate timing models under multiple operating points. Such …
requires timing simulation with accurate timing models under multiple operating points. Such …
Novel test point insertion applications in lbist
Y Sun - 2021 - search.proquest.com
Pseudo-random stimulus for digital test is an established industry practice due to its
simplicity and significant fault coverage. However, when applied to modern circuits, pseudo …
simplicity and significant fault coverage. However, when applied to modern circuits, pseudo …
Diagnosis of Systematic Delay Failures Through Subset Relationship Analysis
BH Hsieh, YS Liu, JCM Li, C Nigh… - 2023 IEEE …, 2023 - ieeexplore.ieee.org
Delay faults have become increasingly important in modern designs due to decreasing
technology node size and increasing operation frequency. However, diagnosis of delay …
technology node size and increasing operation frequency. However, diagnosis of delay …
GPU-accelerated time simulation of systems with adaptive voltage and frequency scaling
Timing validation of systems with adaptive voltage-and frequency scaling (AVFS) requires
an accurate timing model under multiple operating points. Simulating such a model at gate …
an accurate timing model under multiple operating points. Simulating such a model at gate …