An efficient hardware supported and parallelization architecture for intelligent systems to overcome speculative overheads

S Kumar, SK Singh, N Aggarwal… - … Journal of Intelligent …, 2022 - Wiley Online Library
In the last few decades, technology advancements have paved the way for the creation of
intelligent and autonomous systems that utilize complex calculations which are both time …

Transactional locking II

D Dice, O Shalev, N Shavit - International Symposium on Distributed …, 2006 - Springer
The transactional memory programming paradigm is gaining momentum as the approach of
choice for replacing locks in concurrent programming. This paper introduces the …

Memory coherence in shared virtual memory systems

K Li, P Hudak - ACM Transactions on Computer Systems (TOCS), 1989 - dl.acm.org
The memory coherence problem in designing and implementing a shared virtual memory on
loosely coupled multiprocessors is studied in depth. Two classes of algorithms, centralized …

Composable memory transactions

T Harris, S Marlow, S Peyton-Jones… - Proceedings of the tenth …, 2005 - dl.acm.org
Writing concurrent programs is notoriously difficult, and is of increasing practical importance.
A particular source of concern is that even correctly-implemented concurrency abstractions …

LogTM: Log-based transactional memory

KE Moore, J Bobba, MJ Moravan… - … Symposium on High …, 2006 - ieeexplore.ieee.org
Transactional memory (TM) simplifies parallel programming by guaranteeing that
transactions appear to execute atomically and in isolation. Implementing these properties …

An improved construction for counting bloom filters

F Bonomi, M Mitzenmacher, R Panigrahy… - Algorithms–ESA 2006 …, 2006 - Springer
A counting Bloom filter (CBF) generalizes a Bloom filter data structure so as to allow
membership queries on a set that can be changing dynamically via insertions and deletions …

Hybrid transactional memory

P Damron, A Fedorova, Y Lev, V Luchangco… - Proceedings of the 12th …, 2006 - dl.acm.org
Transactional memory (TM) promises to substantially reduce the difficulty of writing correct,
efficient, and scalable concurrent programs. But" bounded" and" best-effort" hardware TM …

McRT-STM: a high performance software transactional memory system for a multi-core runtime

B Saha, AR Adl-Tabatabai, RL Hudson… - Proceedings of the …, 2006 - dl.acm.org
Applications need to become more concurrent to take advantage of the increased
computational power provided by chip level multiprocessing. Programmers have …

Early experience with a commercial hardware transactional memory implementation

D Dice, Y Lev, M Moir, D Nussbaum - Proceedings of the 14th …, 2009 - dl.acm.org
We report on our experience with the hardware transactional memory (HTM) feature of two
pre-production revisions of a new commercial multicore processor. Our experience includes …

[BOG][B] Transactional memory

JR Larus, R Rajwar - 2022 - books.google.com
The advent of multicore processors has renewed interest in the idea of incorporating
transactions into the programming model used to write parallel programs. This approach …