Transformations of high-level synthesis codes for high-performance computing

J de Fine Licht, M Besta, S Meierhans… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
Spatial computing architectures promise a major stride in performance and energy efficiency
over the traditional load/store devices currently employed in large scale computing systems …

Self-aware computing systems

PR Lewis, M Platzner, B Rinner, J Tørresen… - Natural Computing …, 2016 - Springer
This book is the first ever to focus on the emerging field of self-aware computing from an
engineering perspective. It first comprehensively introduces fundamentals for self …

BurstZ+: Eliminating the communication bottleneck of scientific computing accelerators via accelerated compression

G Sun, S Kang, SW Jun - ACM Transactions on Reconfigurable …, 2022 - dl.acm.org
We present BurstZ+, an accelerator platform that eliminates the communication bottleneck
between PCIe-attached scientific computing accelerators and their host servers, via …

BurstZ: a bandwidth-efficient scientific computing accelerator platform for large-scale data

G Sun, S Kang, SW Jun - Proceedings of the 34th ACM International …, 2020 - dl.acm.org
We present BurstZ, a bandwidth-efficient accelerator platform for scientific computing. While
accelerators such as GPUs and FPGAs provide enormous computing capabilities, their …

Automating optimization of reconfigurable designs

M Kurek, T Becker, TCP Chau… - 2014 IEEE 22nd Annual …, 2014 - ieeexplore.ieee.org
We present Automatic Reconfigurable Design Efficient Global Optimization (ARDEGO), a
new algorithm based on the existing Efficient Global Optimization (EGO) methodology for …

Online scheduling and placement of hardware tasks with multiple variants on dynamically reconfigurable field-programmable gate arrays

T Marconi - Computers & Electrical Engineering, 2014 - Elsevier
Hardware task scheduling and placement at runtime plays a crucial role in achieving better
system performance by exploring dynamically reconfigurable Field-Programmable Gate …

Aspect driven compilation for dataflow designs

P Grigoraş, X Niu, JGF Coutinho, W Luk… - 2013 IEEE 24th …, 2013 - ieeexplore.ieee.org
This paper proposes a novel hardware compilation approach targeting dataflow designs.
This approach is based on aspect-oriented programming to decouple design development …

Knowledge transfer in automatic optimisation of reconfigurable designs

M Kurek, MP Deisenroth, W Luk… - 2016 IEEE 24th Annual …, 2016 - ieeexplore.ieee.org
This paper presents a novel approach for automatic optimisation of reconfigurable design
parameters based on knowledge transfer. The key idea is to make use of insights derived …

Automating elimination of idle functions by runtime reconfiguration

X Niu, TCP Chau, Q **, W Luk, Q Liu… - ACM Transactions on …, 2015 - dl.acm.org
A design approach is proposed to automatically identify and exploit runtime reconfiguration
opportunities with optimised resource utilisation by eliminating idle functions. We introduce …

Reference architecture for self-aware and self-expressive computing systems

A Chandra, PR Lewis, K Glette, SC Stilkerich - Self-Aware Computing …, 2016 - Springer
This chapter covers a reference architecture for describing and engineering computational
self-awareness and self-expression in computing systems. The architecture provides a …