SoK: Computer-aided cryptography

M Barbosa, G Barthe, K Bhargavan… - … IEEE symposium on …, 2021 - ieeexplore.ieee.org
Computer-aided cryptography is an active area of research that develops and applies
formal, machine-checkable approaches to the design, analysis, and implementation of …

Spectector: Principled detection of speculative information flows

M Guarnieri, B Köpf, JF Morales… - … IEEE Symposium on …, 2020 - ieeexplore.ieee.org
Since the advent of Spectre, a number of counter-measures have been proposed and
deployed. Rigorously reasoning about their effectiveness, however, requires a well-defined …

Hardware-software contracts for secure speculation

M Guarnieri, B Köpf, J Reineke… - 2021 IEEE Symposium on …, 2021 - ieeexplore.ieee.org
Since the discovery of Spectre, a large number of hardware mechanisms for secure
speculation has been proposed. Intuitively, more defensive mechanisms are less efficient …

Scaling symbolic evaluation for automated verification of systems code with Serval

L Nelson, J Bornholt, R Gu, A Baumann… - Proceedings of the 27th …, 2019 - dl.acm.org
This paper presents Serval, a framework for develo** automated verifiers for systems
software. Serval provides an extensible infrastructure for creating verifiers by lifting …

QED at large: A survey of engineering of formally verified software

T Ringer, K Palmskog, I Sergey… - … and Trends® in …, 2019 - nowpublishers.com
Abstract Development of formal proofs of correctness of programs can increase actual and
perceived reliability and facilitate better understanding of program specifications and their …

A complete formal semantics of x86-64 user-level instruction set architecture

S Dasgupta, D Park, T Kasampalis, VS Adve… - Proceedings of the 40th …, 2019 - dl.acm.org
We present the most complete and thoroughly tested formal semantics of x86-64 to date. Our
semantics faithfully formalizes all the non-deprecated, sequential user-level instructions of …

Capability hardware enhanced RISC instructions: CHERI instruction-set architecture (version 7)

RNM Watson, PG Neumann, J Woodruff, M Roe… - 2019 - cl.cam.ac.uk
This technical report describes CHERI ISAv7, the seventh version of the Capability
Hardware Enhanced RISC Instructions (CHERI) Instruction-Set Architecture (ISA) being …

Specification and verification of side-channel security for open-source processors via leakage contracts

Z Wang, G Mohr, K von Gleissenthall… - Proceedings of the …, 2023 - dl.acm.org
Leakage contracts have recently been proposed as a new security abstraction at the
Instruction Set Architecture (ISA) level. Leakage contracts aim to capture the information that …

Revizor: Testing black-box CPUs against speculation contracts

O Oleksenko, C Fetzer, B Köpf… - Proceedings of the 27th …, 2022 - dl.acm.org
Speculative vulnerabilities such as Spectre and Meltdown expose speculative execution
state that can be exploited to leak information across security domains via side-channels …

A survey on risc-v security: Hardware and architecture

T Lu - arxiv preprint arxiv:2107.04175, 2021 - arxiv.org
The Internet of Things (IoT) is an ongoing technological revolution. Embedded processors
are the processing engines of smart IoT devices. For decades, these processors were …