Advances in IC fabrication technology, coupled with aggressive circuit design, have led to
exponential growth of IC speed and integration levels. For these improvements to benefit …

57 ABSTRACT A method and circuit adaptively adjust the timing offset of a digital Signal
relative to a clock signal output coincident with that digital Signal to enable a latch receiving …

A integrated circuit, such as a memory integrated circuit, includes a vernier clock adjustment
circuit receiving an input clock signal and providing a rising-edge clock signal representing …

21/Egg}? et a1 ' A synchronous clock generator is comprised of a delay 4'6OO'895 7; 1986
Laflldlsr'r'lgri"""" 331% A locked loop for producing a plurality of signals in …

US6026050A - Method and apparatus for adaptively adjusting the timing of a clock signal used
to latch digital signals, and memory device using same - Google Patents US6026050A …

A high speed CMOS signaling interface for application in multiprocessor interconnection
networks has been developed. The interface utilizes IV push-pull drivers, a delay line phase …

The achievable off-chip bandwidth of digital IC's is a crucial and often limiting factor in the
performance of digital systems. In intra-system interfaces where both latency and bandwidth …

(57) ABSTRACT A bus capture circuit captures digital Signals applied on respective lines of
a bus. The bus capture circuit includes a clock delay circuit that generates an internal clock …

Clock alignment circuits and techniques for reducing power dissipation, increasing power
supply noise immunity, decreasing process and temperature variation sensitivity, and …

57 ABSTRACT A delay-locked loop incorporates binary-coupled capacitors in a capacitor
bank to produce a variable capacitance along a delay line. The variable capacitance allows …