Germanium CMOS potential from material and process perspectives: Be more positive about germanium
CMOS miniaturization is now approaching the sub-10 nm level, and further downscaling is
expected. This size scaling will end sooner or later, however, because the typical size is …
expected. This size scaling will end sooner or later, however, because the typical size is …
High-Mobility Ge p- and n-MOSFETs With 0.7-nm EOT Using Gate Stacks Fabricated by Plasma Postoxidation
R Zhang, PC Huang, JC Lin, N Taoka… - … on Electron Devices, 2013 - ieeexplore.ieee.org
An ultrathin equivalent oxide thickness (EOT) HfO 2/Al 2 O 3/Ge gate stack has been
fabricated by combining the plasma postoxidation method with a 0.2-nm-thick Al 2 O 3 layer …
fabricated by combining the plasma postoxidation method with a 0.2-nm-thick Al 2 O 3 layer …
Ultimate nano-electronics: New materials and device concepts for scaling nano-electronics beyond the Si roadmap
In this work, we will give an overview of the innovations in materials and new device
concepts that will be needed to continue Moore's law to the sub-10 nm technology nodes. To …
concepts that will be needed to continue Moore's law to the sub-10 nm technology nodes. To …
7-nm FinFET CMOS design enabled by stress engineering using Si, Ge, and Sn
S Gupta, V Moroz, L Smith, Q Lu… - IEEE transactions on …, 2014 - ieeexplore.ieee.org
Bandgap and stress engineering using group IV materials-Si, Ge, and Sn, and their alloys
are employed to design a FinFET-based CMOS solution for the 7-nm technology node and …
are employed to design a FinFET-based CMOS solution for the 7-nm technology node and …
Ge CMOS gate stack and contact development for vertically stacked lateral nanowire FETs
We present (i) a novel, thermally stable Atomic Layer Deposition (ALD) high-k dielectric
stack that, for the first time, has the potential to meet all gate stack requirements for both n …
stack that, for the first time, has the potential to meet all gate stack requirements for both n …
Aggressive EOT Scaling of Ge pMOSFETs With HfO2/AlOx/GeOx Gate-Stacks Fabricated by Ozone Postoxidation
HfO 2/AlO x/GeO x gate-stacks have been fabricated on Ge surfaces by in situ ozone
postoxidation method. It is found that the ultrathin GeOx interfacial layer beneath the high-k …
postoxidation method. It is found that the ultrathin GeOx interfacial layer beneath the high-k …
III-V/Ge MOS device technologies for low power integrated systems
CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of the
promising devices for high performance and low power integrated systems in the future …
promising devices for high performance and low power integrated systems in the future …
Understanding the suppressed charge trap** in relaxed- and strained-Ge/SiO2/HfO2 pMOSFETs and implications for the screening of alternative high-mobility …
We study charge trap** in a variety of Ge-based pMOS and nMOS technologies, either
with Si passivation and conventional SiO 2/HfO 2 gate stack, or with GeO x/high-k gate …
with Si passivation and conventional SiO 2/HfO 2 gate stack, or with GeO x/high-k gate …
Slow Trap Properties and Generation in Al2O3/GeOx/Ge MOS Interfaces Formed by Plasma Oxidation Process
For realizing Ge CMOS devices with a small equivalent oxide thickness (EOT) and a low
density of fast interface states (D it), understanding of slow traps in Ge gate stacks and …
density of fast interface states (D it), understanding of slow traps in Ge gate stacks and …
Improved Electrical Characteristics of Ge pMOSFETs With ZrO2/HfO2 Stack Gate Dielectric
CC Li, KS Chang-Liao, WF Chi, MC Li… - IEEE Electron …, 2015 - ieeexplore.ieee.org
Electrical characteristics of Ge pMOSFETs with HfO 2, ZrO 2, ZrO 2/HfO 2, and HfZrO x gate
dielectrics are studied in this letter. A lower equivalent oxide thickness (EOT) is obtained in …
dielectrics are studied in this letter. A lower equivalent oxide thickness (EOT) is obtained in …