[BOOK][B] Processor description languages
Efficient design of embedded processors plays a critical role in embedded systems design.
Processor description languages and their associated specification, exploration and rapid …
Processor description languages and their associated specification, exploration and rapid …
Understanding the GPU microarchitecture to achieve bare-metal performance tuning
In this paper, we present a methodology to understand GPU microarchitectural features and
improve performance for compute-intensive kernels. The methodology relies on a reverse …
improve performance for compute-intensive kernels. The methodology relies on a reverse …
ISAMAP: instruction map** driven by dynamic binary translation
M Souza, D Nicácio, G Araújo - International Symposium on Computer …, 2010 - Springer
Abstract Dynamic Binary Translation (DBT) techniques have been largely used in the
migration of legacy code and in the transparent execution of programs across different …
migration of legacy code and in the transparent execution of programs across different …
[PDF][PDF] Reconfigurable architectures for embedded systems
H Svensson - 2008 - cdworkshop.eit.lth.se
Application-specific circuits are used to migrate computer systems from workstations to
handheld devices that need real-time performance within the budget for physical size and …
handheld devices that need real-time performance within the budget for physical size and …
Describing and Simulating Dynamic Reconfiguration in SystemC Exemplified by a Dedicated 3D Collision Detection Hardware
A Raabe - 2008 - bonndoc.ulb.uni-bonn.de
The ongoing trend towards development of parallel software and the increased flexibility of
state-of-the-art programmable logic devices are currently converging in the field of …
state-of-the-art programmable logic devices are currently converging in the field of …
A flexible platform framework for rapid transactional memory systems prototy** and evaluation
Transactional memory (TM) is an emerging synchronization mechanism that aims to solve
most of the difficulties inherent in lock-based approaches. TM implementations may either …
most of the difficulties inherent in lock-based approaches. TM implementations may either …
Automatic link editor generation for embedded CPU cores
SoC design space exploration requires code generation for several CPU core alternatives.
However, an embedded software code generation toolkit cannot be developed from scratch …
However, an embedded software code generation toolkit cannot be developed from scratch …
Design and Implementation of Binary Utilities Generator
JQ Shen, J Wu, ZF Zhang, HQ Ren - Applied Mechanics and …, 2014 - Trans Tech Publ
This paper presents a framework for generating assembler and disassembler from ADL
(architecture description language), which enables processor architecture designers to …
(architecture description language), which enables processor architecture designers to …
[PDF][PDF] Implementace obecného assembleru
A Husár, INGT HRUŠKA - 2007 - theses.cz
This thesis describes the design of the universal assembler that represents a part of the
Lissom project. You will be provided with the description of the assembler architectures and …
Lissom project. You will be provided with the description of the assembler architectures and …
[PDF][PDF] Automatic adl-based generation of disassembling tools
AKI Mendonça, FG Carvalho, MRO Schultz… - sort, 2006 - sbmicro.org.br
Embedded software evaluation for distinct CPU targets is required during SoC design space
exploration. To cope with time-to-market, such exploration asks for automatically …
exploration. To cope with time-to-market, such exploration asks for automatically …