The general objective of our work is to investigate the area and power-delay performances
of low-voltage full adder cells in different CMOS logic styles for the predominating tree …

We present a new design for a 1-b full adder featuring hybrid-CMOS design style. The quest
to achieve a good-drivability, noise-robustness, and low-energy operations for deep …

Modern digital circuits are facing aggressive technology and voltage scaling under
emerging technology generations. This study proposes a circuit‐level technique to mitigate …

In this paper we present two novel 1-bit full adder cells in dynamic logic style. NP-CMOS
(Zipper) and Multi-Output structures are used to design the adder blocks. Characteristic of …

In this paper, we propose a systematic design methodology based on transmission gate in
the category of hybrid-CMOS Logic style. We start by with selecting a basic cell including two …

A new transistor sizing algorithm, SEA (Simple Exact Algorithm), for optimizing low‐power
and high‐speed arithmetic integrated circuits is proposed. In comparison with other …

This exploratory study on vertical, undoped silicon nanowire transistors shows less power
dissipation with respect to the bulk and SOI MOS transistors while yielding comparable …

In this paper, we propose a systematic design methodology in the category of hybrid-CMOS
logic style. Our methodology is based on using different basic cells and optimizations. We …

In this paper, we propose a systematic design methodology in the category of hybrid-CMOS
logic style. A huge library of circuits appropriate for low-power and high-speed applications …

Full adder is among the most practical logic blocks. It is the main arithmetical component of
all digital systems. This paper presents the novel design of a high-speed and high-efficient …