A survey of architectural approaches for data compression in cache and main memory systems
As the number of cores on a chip increases and key applications become even more data-
intensive, memory systems in modern processors have to deal with increasingly large …
intensive, memory systems in modern processors have to deal with increasingly large …
Overcoming the challenges of crossbar resistive memory architectures
The scalability of DRAM faces challenges from increasing power consumption and the
difficulty of building high aspect ratio capacitors. Consequently, emerging memory …
difficulty of building high aspect ratio capacitors. Consequently, emerging memory …
Approximate communication: Techniques for reducing communication bottlenecks in large-scale parallel systems
Approximate computing has gained research attention recently as a way to increase energy
efficiency and/or performance by exploiting some applications' intrinsic error resiliency …
efficiency and/or performance by exploiting some applications' intrinsic error resiliency …
Understanding reduced-voltage operation in modern DRAM devices: Experimental characterization, analysis, and mechanisms
The energy consumption of DRAM is a critical concern in modern computing systems.
Improvements in manufacturing process technology have allowed DRAM vendors to lower …
Improvements in manufacturing process technology have allowed DRAM vendors to lower …
VAULT: Reducing paging overheads in SGX with efficient integrity verification structures
M Taassori, A Shafiee… - Proceedings of the Twenty …, 2018 - dl.acm.org
Intel's SGX offers state-of-the-art security features, including confidentiality, integrity, and
authentication (CIA) when accessing sensitive pages in memory. Sensitive pages are …
authentication (CIA) when accessing sensitive pages in memory. Sensitive pages are …
Adaptive-latency DRAM: Optimizing DRAM timing for the common-case
In current systems, memory accesses to a DRAM chip must obey a set of minimum latency
restrictions specified in the DRAM standard. Such timing parameters exist to guarantee …
restrictions specified in the DRAM standard. Such timing parameters exist to guarantee …
Morphable counters: Enabling compact integrity trees for low-overhead secure memories
Securing off-chip main memory is essential for protection from adversaries with physical
access to systems. However, current secure-memory designs incur considerable …
access to systems. However, current secure-memory designs incur considerable …
Warped-compression: Enabling power efficient GPUs through register compression
This paper presents Warped-Compression, a warp-level register compression scheme for
reducing GPU power consumption. This work is motivated by the observation that the …
reducing GPU power consumption. This work is motivated by the observation that the …
Daemon: Architectural support for efficient data movement in fully disaggregated systems
Resource disaggregation offers a cost effective solution to resource scaling, utilization, and
failure-handling in data centers by physically separating hardware devices in a server …
failure-handling in data centers by physically separating hardware devices in a server …
Bit-plane compression: Transforming data for better compression in many-core architectures
As key applications become more data-intensive and the computational throughput of
processors increases, the amount of data to be transferred in modern memory subsystems …
processors increases, the amount of data to be transferred in modern memory subsystems …