A survey of architectural approaches for data compression in cache and main memory systems

S Mittal, JS Vetter - IEEE Transactions on Parallel and …, 2015 - ieeexplore.ieee.org
As the number of cores on a chip increases and key applications become even more data-
intensive, memory systems in modern processors have to deal with increasingly large …

Overcoming the challenges of crossbar resistive memory architectures

C Xu, D Niu, N Muralimanohar… - 2015 IEEE 21st …, 2015 - ieeexplore.ieee.org
The scalability of DRAM faces challenges from increasing power consumption and the
difficulty of building high aspect ratio capacitors. Consequently, emerging memory …

Approximate communication: Techniques for reducing communication bottlenecks in large-scale parallel systems

F Betzel, K Khatamifard, H Suresh, DJ Lilja… - ACM Computing …, 2018 - dl.acm.org
Approximate computing has gained research attention recently as a way to increase energy
efficiency and/or performance by exploiting some applications' intrinsic error resiliency …

Understanding reduced-voltage operation in modern DRAM devices: Experimental characterization, analysis, and mechanisms

KK Chang, AG Yağlıkçı, S Ghose, A Agrawal… - Proceedings of the …, 2017 - dl.acm.org
The energy consumption of DRAM is a critical concern in modern computing systems.
Improvements in manufacturing process technology have allowed DRAM vendors to lower …

VAULT: Reducing paging overheads in SGX with efficient integrity verification structures

M Taassori, A Shafiee… - Proceedings of the Twenty …, 2018 - dl.acm.org
Intel's SGX offers state-of-the-art security features, including confidentiality, integrity, and
authentication (CIA) when accessing sensitive pages in memory. Sensitive pages are …

Adaptive-latency DRAM: Optimizing DRAM timing for the common-case

D Lee, Y Kim, G Pekhimenko, S Khan… - 2015 IEEE 21st …, 2015 - ieeexplore.ieee.org
In current systems, memory accesses to a DRAM chip must obey a set of minimum latency
restrictions specified in the DRAM standard. Such timing parameters exist to guarantee …

Morphable counters: Enabling compact integrity trees for low-overhead secure memories

G Saileshwar, PJ Nair, P Ramrakhyani… - 2018 51st Annual …, 2018 - ieeexplore.ieee.org
Securing off-chip main memory is essential for protection from adversaries with physical
access to systems. However, current secure-memory designs incur considerable …

Warped-compression: Enabling power efficient GPUs through register compression

S Lee, K Kim, G Koo, H Jeon, WW Ro… - ACM SIGARCH …, 2015 - dl.acm.org
This paper presents Warped-Compression, a warp-level register compression scheme for
reducing GPU power consumption. This work is motivated by the observation that the …

Daemon: Architectural support for efficient data movement in fully disaggregated systems

C Giannoula, K Huang, J Tang, N Koziris… - Proceedings of the …, 2023 - dl.acm.org
Resource disaggregation offers a cost effective solution to resource scaling, utilization, and
failure-handling in data centers by physically separating hardware devices in a server …

Bit-plane compression: Transforming data for better compression in many-core architectures

J Kim, M Sullivan, E Choukse, M Erez - ACM SIGARCH Computer …, 2016 - dl.acm.org
As key applications become more data-intensive and the computational throughput of
processors increases, the amount of data to be transferred in modern memory subsystems …