[BOK][B] Multiprocessor systems-on-chips

A Jerraya, W Wolf - 2004 - books.google.com
Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple
processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) …

Tiling optimizations for 3D scientific computations

G Rivera, CW Tseng - SC'00: Proceedings of the 2000 ACM …, 2000 - ieeexplore.ieee.org
Compiler transformations can significantly improve data locality for many scientific programs.
In this paper, we show iterative solvers for partial differential equations (PDEs) in three …

[PDF][PDF] Reuse distance as a metric for cache behavior

K Beyls, E D'Hollander - Proceedings of the IASTED Conference on …, 2001 - Citeseer
The widening gap between memory and processor speed causes more and more programs
to shift from CPU-bounded to memory speed-bounded, even in the presence of multi-level …

[BOK][B] The compiler design handbook: optimizations and machine code generation

YN Srikant, P Shankar - 2002 - taylorfrancis.com
The widespread use of object-oriented languages and Internet security concerns are just the
beginning. Add embedded systems, multiple memory banks, highly pipelined units …

[BOK][B] Data access and storage management for embedded programmable processors

F Catthoor, K Danckaert - 2002 - books.google.com
Data Access and Storage Management for Embedded Programmable Processors gives an
overview of the state-of-the-art in system-level data access and storage management for …

[BOK][B] Embedded systems design: the ARTIST roadmap for research and development

B Bouyssounouse - 2005 - books.google.com
Embedded systems now include a very large proportion of the advanced products designed
in the world, spanning transport (avionics, space, automotive, trains), electrical and …

Tiling, block data layout, and memory hierarchy performance

N Park, B Hong, VK Prasanna - IEEE Transactions on Parallel …, 2003 - ieeexplore.ieee.org
Recently, several experimental studies have been conducted on block data layout in
conjunction with tiling as a data transformation technique to improve cache performance. In …

Automatic tiling of iterative stencil loops

Z Li, Y Song - ACM Transactions on Programming Languages and …, 2004 - dl.acm.org
Iterative stencil loops are used in scientific programs to implement relaxation methods for
numerical simulation and signal processing. Such loops iteratively modify the same array …

Accelerating XOR-based erasure coding using program optimization techniques

Y Uezato - Proceedings of the International Conference for High …, 2021 - dl.acm.org
Erasure coding (EC) affords data redundancy for large-scale systems. XOR-based EC is an
easy-to-implement method for optimizing EC. This paper addresses a significant …

Locality analysis through static parallel sampling

D Chen, F Liu, C Ding, S Pai - ACM SIGPLAN Notices, 2018 - dl.acm.org
Locality analysis is important since accessing memory is much slower than computing.
Compile-time locality analysis can provide detailed program-level feedback for compilers or …