Disclosed herein are exemplary embodiments of a so-called “X-press” test response
compactor. Certain embodiments of the disclosed compactor comprise an overdrive section …

US PATENT DOCUMENTS FOREIGN PATENT DOCUMENTS 5,642,362 A 6, 1997 Savir EP
O 549. 949 3, 1998 5,680,543 A 10, 1997 Bhawmik JP 63-286780 11, 1988 5,694.402 A …

US7925465B2 - Low power scan testing techniques and apparatus - Google Patents
US7925465B2 - Low power scan testing techniques and apparatus - Google Patents Low power …

Roughly described, a scan-based test architecture is opti mized in dependence upon the
circuit design under consider ation. In one embodiment, a plurality of candidate test designs …

Provisional application No. 60/774,431, filed on Feb.(57) 17, 2006, provisional application
No. 60/832,466, Disclosed herein are exemplary embodiments of a so-called filed on Jul …

A test system tests a circuit. Compressed scan data subsets are stored, one at a time, in a
memory of the test system. The multiple compressed scan data subsets correspond with …

(57) ABSTRACT A method for processing a sequence of fault messages occur ring in a
device including many systems, makes it possible to discriminate between fault messages …

SUMMARY OF THE INVENTION A first aspect of the present invention is a method of testing
integrated circuits, comprising: determining paths of an inte grated circuit, the path …

Test patterns for at-speed scan tests are generated by filling unspecified bits of test cubes
with functional background data. Functional background data are scan cell values observed …

Roughly described, a scan-based test architecture is opti mized in dependence upon the
circuit design under consider ation. In one embodiment, a plurality of candidate test designs …