Formation of a silicon oxynitride layer on a high-k dielectric material

PK Narwankar, G Higashi - US Patent 8,119,210, 2012 - Google Patents
(52) US Cl........................................................ 427/569 (57) ABSTRACT (58) Field of
Classification Search................... 427/569 In one embodiment, a method for depositing a …

ALD metal oxide deposition process using direct oxidation

CR Metzner, SS Kher, V Gopal, S Han… - US Patent …, 2009 - Google Patents
(57) Embodiments of the invention provide methods for forming hafnium materials, such as
oxides and nitrides, by sequen tially exposing a Substrate to hafnium precursors and active …

Method of enabling seamless cobalt gap-fill

AV Gelatos, B Zheng, Y Lei, X Fu, S Gandikota… - US Patent …, 2016 - Google Patents
Methods for depositing a contact metal layer in contact struc tures of a semiconductor device
are provided. In one embodi ment, a method for depositing a contact metal layer for form ing …

Method for fabricating an integrated gate dielectric layer for field effect transistors

TC Chua, S Muthukrisnan, J Swenberg, S Kher… - US Patent …, 2009 - Google Patents
Methods for forming a integrated gate dielectric layer on a substrate are provided. In one
embodiment, the method includes forming a silicon oxide layer on a substrate, plasma …

High pressure wafer processing systems and related methods

Q Liang, SD Nemani, A Khan, VR Kasibhotla… - US Patent …, 2025 - Google Patents
A high-pressure processing system for processing a substrate includes a first chamber, a
pedestal positioned within the first chamber to support the substrate, a second chamber …

Processing multilayer semiconductors with multiple heat sources

S Ramamurthy, AG Hegedus, R Thakur - US Patent 8,536,492, 2013 - Google Patents
A method and apparatus for rapid thermal annealing compris ing a plurality of lamps affixed
to a lid of the chamber that provide at least one wavelength of light, a laser source extend …

Pulse train annealing method and apparatus

S Moffatt, JM Ranish - US Patent App. 12/203,696, 2009 - Google Patents
(57) ABSTRACT Correspondence Address: PATTERSON & SHERIDAN, LLP--APPM/TX The
present invention generally describes apparatuses and 3040 POST OAKBOULEVARD …

Method of fabricating a high dielectric constant transistor gate using a low energy plasma apparatus

TC Chua, AM Paterson, S Hung, PM Liu, T Sato… - US Patent …, 2010 - Google Patents
US7837838B2 - Method of fabricating a high dielectric constant transistor gate using a low
energy plasma apparatus - Google Patents US7837838B2 - Method of fabricating a high …

Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system

CS Olsen, TC Chua, S Hung, PM Liu, T Sato… - US Patent …, 2010 - Google Patents
US7645710B2 - Method and apparatus for fabricating a high dielectric constant transistor gate
using a low energy plasma system - Google Patents US7645710B2 - Method and apparatus …

Pulse train annealing method and apparatus

S Moffatt, JM Ranish - US Patent 7,800,081, 2010 - Google Patents
110 imparted by each pulse to dissipate completely. Thus, each pulse completes a micro-
anneal cycle. The pulses may be delivered to the entire substrate at once, or to portions of …