FPGA-based accelerators of deep learning networks for learning and classification: A review
Due to recent advances in digital technologies, and availability of credible data, an area of
artificial intelligence, deep learning, has emerged and has demonstrated its ability and …
artificial intelligence, deep learning, has emerged and has demonstrated its ability and …
IronMan-Pro: Multiobjective design space exploration in HLS via reinforcement learning and graph neural network-based modeling
Despite the great success of high-level synthesis (HLS) tools, we observe several
unresolved challenges: 1) the high-level abstraction of HLS programming styles sometimes …
unresolved challenges: 1) the high-level abstraction of HLS programming styles sometimes …
MALOC: A fully pipelined FPGA accelerator for convolutional neural networks with all layers mapped on chip
Recently, field-programmable gate arrays (FPGAs) have been widely used in the
implementations of hardware accelerator for convolutional neural networks (CNNs) …
implementations of hardware accelerator for convolutional neural networks (CNNs) …
IRONMAN GNN-assisted Design Space Exploration in High-Level Synthesis via Reinforcement Learning
Despite the great success of High-Level Synthesis (HLS) tools, we observe several
unresolved challenges: 1) the high-level abstraction of programming styles in HLS conceals …
unresolved challenges: 1) the high-level abstraction of programming styles in HLS conceals …
Polyhedral-based data reuse optimization for configurable computing
Many applications, such as medical imaging, generate intensive data traffic between the
FPGA and off-chip memory. Significant improvements in the execution time can be achieved …
FPGA and off-chip memory. Significant improvements in the execution time can be achieved …
Combining dynamic & static scheduling in high-level synthesis
A central task in high-level synthesis is scheduling: the allocation of operations to clock
cycles. The classic approach to scheduling is static, in which each operation is mapped to a …
cycles. The classic approach to scheduling is static, in which each operation is mapped to a …
Aha: An agile approach to the design of coarse-grained reconfigurable accelerators and compilers
With the slowing of Moore's law, computer architects have turned to domain-specific
hardware specialization to continue improving the performance and efficiency of computing …
hardware specialization to continue improving the performance and efficiency of computing …