Multilayer obstacle-avoiding X-architecture Steiner minimal tree construction based on particle swarm optimization
G Liu, X Huang, W Guo, Y Niu… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
As the basic model for very large scale integration routing, the Steiner minimal tree (SMT)
can be used in various practical problems, such as wire length optimization, congestion, and …
can be used in various practical problems, such as wire length optimization, congestion, and …
Consumer electronics product manufacturing time reduction and optimization using AI-based PCB and VLSI circuit designing
Y Goh, D Jung, G Hwang… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
Circuit design plays an essential role in all consumer electronics products. Printed circuit
board (PCB) and very-large-scale integration (VLSI) circuit designing requires optimization …
board (PCB) and very-large-scale integration (VLSI) circuit designing requires optimization …
Obstacle-avoiding algorithm in X-architecture based on discrete particle swarm optimization for VLSI design
X Huang, G Liu, W Guo, Y Niu, G Chen - ACM Transactions on Design …, 2015 - dl.acm.org
Obstacle-avoiding Steiner minimal tree (OASMT) construction has become a focus problem
in the physical design of modern very large-scale integration (VLSI) chips. In this article, an …
in the physical design of modern very large-scale integration (VLSI) chips. In this article, an …
Optimal interconnection trees in the plane
Physical networks are pervasive in our society. They range from the traditional copper
networks in telecommunications to the modern optical cable networks used for broadband …
networks in telecommunications to the modern optical cable networks used for broadband …
A survey on steiner tree construction and global routing for vlsi design
Global Routing (GR) is a crucial and complex stage in the Very Large-Scale Integration
(VLSI) design, which minimizes interconnect wirelength and delay to optimize the overall …
(VLSI) design, which minimizes interconnect wirelength and delay to optimize the overall …
FH-OAOS: A fast four-step heuristic for obstacle-avoiding octilinear Steiner tree construction
X Huang, W Guo, G Liu, G Chen - ACM Transactions on Design …, 2016 - dl.acm.org
With the sharp increase of very large-scale integrated (VLSI) circuit density, we are faced
with many knotty issues. Particularly in the routing phase of VLSI physical design, the …
with many knotty issues. Particularly in the routing phase of VLSI physical design, the …
NN-Steiner: A mixed neural-algorithmic approach for the rectilinear Steiner minimum tree problem
Recent years have witnessed rapid advances in the use of neural networks to solve
combinatorial optimization problems. Nevertheless, designing the" right" neural model that …
combinatorial optimization problems. Nevertheless, designing the" right" neural model that …
An efficient obstacle-avoiding rectilinear Steiner tree construction method using PB-SAT
Rectilinear Steiner tree (RST) construction is an important part of recent VLSI physical
design. This article presents an efficient satisfiability (SAT) based approach to construct an …
design. This article presents an efficient satisfiability (SAT) based approach to construct an …
An efficient bi-criteria flow channel routing algorithm for flow-based microfluidic biochips
Rapid growth in capacity makes flow-based microfluidic biochips a promising candidate for
biochemical analysis because they can integrate more complex functions. However, as the …
biochemical analysis because they can integrate more complex functions. However, as the …
A reinforcement learning agent for obstacle-avoiding rectilinear steiner tree construction
PY Chen, BT Ke, TC Lee, IC Tsai, TW Kung… - Proceedings of the …, 2022 - dl.acm.org
This paper presents a router, which tackles a classic algorithm problem in EDA, obstacle-
avoiding rectilinear Steiner minimum tree (OARSMT), with the help of an agent trained by …
avoiding rectilinear Steiner minimum tree (OARSMT), with the help of an agent trained by …