Semiconductor memory device having a stepped structure and contact wirings formed thereon
T Inatsuka - US Patent 10,134,672, 2018 - Google Patents
A semiconductor storage device includes a substrate, a stack of first insulating layers and
conductive layers that are alternately formed on the substrate in a memory region and a …
conductive layers that are alternately formed on the substrate in a memory region and a …
Interconnect structure of three-dimensional memory device
Z Lu, S Lidong, LI Yongna, F Pan, SW Yang… - US Patent …, 2021 - Google Patents
Embodiments of interconnect structures of a three-dimen sional (3D) memory device and
method for forming the interconnect structures are disclosed. In an example, a 3D NAND …
method for forming the interconnect structures are disclosed. In an example, a 3D NAND …
Three-dimensional memory device and manufacturing method thereof
ZL Huo, M Liu, L ** - US Patent 10,475,807, 2019 - Google Patents
A method for manufacturing three-dimensional memory, comprising the steps of: forming a
stack structure composed of a plurality of first material layers and a plurality of second …
stack structure composed of a plurality of first material layers and a plurality of second …
Semiconductor apparatus
JH Song, SM Jo - US Patent 9,837,349, 2017 - Google Patents
A semiconductor apparatus includes gate electrodes and interlayer insulating layers
alternately stacked on a substrate, channel regions penetrating through the gate electrodes …
alternately stacked on a substrate, channel regions penetrating through the gate electrodes …
Methods of manufacturing vertical semiconductor devices
BK You, KS Seol, Y Park, JS Lim - US Patent 8,697,524, 2014 - Google Patents
Methods of manufacturing vertical semiconductor devices may include forming a mold
structure including sacrificial layers and insulating interlayers with a first opening formed …
structure including sacrificial layers and insulating interlayers with a first opening formed …
Methods and apparatuses having memory cells including a monolithic semiconductor channel
J Sun, Z Lu, RW Lindsay, B Cleereman… - US Patent …, 2016 - Google Patents
Methods for forming a string of memory cells, apparatuses having a string of memory cells,
and systems are disclosed. One such method for forming a string of memory cells forms a …
and systems are disclosed. One such method for forming a string of memory cells forms a …
Multiple mold structure methods of manufacturing vertical memory devices
(57) ABSTRACT A first insulating interlayer is formed on a substrate including first and
second regions. The first insulating interlayer has top surface, a height of which is greater in …
second regions. The first insulating interlayer has top surface, a height of which is greater in …
Three-dimensional semiconductor device having contact plugs penetrating upper adjacent electrodes
HM Park - US Patent 10,396,035, 2019 - Google Patents
A three-dimensional semiconductor device includes: a substrate having a cell array region
and a contact region; a stacked structure including a plurality of electrodes and a plurality of …
and a contact region; a stacked structure including a plurality of electrodes and a plurality of …
Methods and apparatuses having strings of memory cells including a metal source
Z Lu, RW Lindsay, A Bicksler, YJ Hu, H Liu - US Patent 9,437,604, 2016 - Google Patents
Methods for forming a string of memory cells, an apparatus having a string of memory cells,
and a system are disclosed. A method for forming the string of memory cells comprises …
and a system are disclosed. A method for forming the string of memory cells comprises …
Semiconductor memory device and method of manufacturing the same
BO Kim, JT Noh, SJ Shin, JY Ahn, KH Hwang - US Patent 9,530,899, 2016 - Google Patents
A semiconductor device and a method of manufacturing the same are provided. The
semiconductor device includes insulation layers and gate electrodes alternately stacked on …
semiconductor device includes insulation layers and gate electrodes alternately stacked on …