Advanced system analysis and survey on the GPS receiver front end

A Kumari, D Bhatt - IEEE Access, 2022 - ieeexplore.ieee.org
A fully integrated GPS receiver system can enable unique system capabilities by
synthesizing both receiver front end and baseband on the same chip, leading to lower area …

A comprehensive analysis of IMD behavior in RF CMOS power amplifiers

C Fager, JC Pedro, NB de Carvalho… - IEEE journal of solid …, 2004 - ieeexplore.ieee.org
This paper presents a comprehensive analysis of nonlinear intermodulation distortion (IMD)
behavior in RF CMOS power amplifiers (PAs). Separate analyses are presented for small …

A 19-mW 2.6-mm/sup 2/L1/L2 dual-band CMOS GPS receiver

J Ko, J Kim, S Cho, K Lee - IEEE Journal of Solid-State Circuits, 2005 - ieeexplore.ieee.org
This paper presents the design and implementation of an L1/L2 dual-band global
positioning system (GPS) receiver. Dual-conversion with a low-IF architecture was used for …

A 72-mW CMOS 802.11 a direct conversion front-end with 3.5-dB NF and 200-kHz 1/f noise corner

M Valla, G Montagna, R Castello… - IEEE Journal of Solid …, 2005 - ieeexplore.ieee.org
A direct conversion 802.11 a receiver front-end including a synthesizer with quadrature VCO
has been integrated in a 0.13-/spl mu/m CMOS process. The chip has an active area of 1.8 …

A complete single-chip GPS receiver with 1.6-V 24-mW radio in 0.18-/spl mu/m CMOS

T Kadoyama, N Suzuki, N Sasho… - IEEE Journal of Solid …, 2004 - ieeexplore.ieee.org
We have developed a complete single-chip GPS receiver using 0.18-/spl mu/m CMOS to
meet several important requirements, such as small size, low power, low cost, and high …

A 1-MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers

F Henkel, U Langmann, A Hanke… - IEEE Journal of Solid …, 2002 - ieeexplore.ieee.org
This paper presents a quadrature bandpass/spl Sigma//spl Delta/modulator with continuous-
time architecture. Due to the continuous-time architecture and the inherent anti-aliasing filter …

A 56-mW 23-mm/sup 2/single-chip 180-nm CMOS GPS receiver with 27.2-mW 4.1-mm/sup 2/radio

G Gramegna, PG Mattos, M Losi, S Das… - IEEE Journal of Solid …, 2006 - ieeexplore.ieee.org
A 56-mW 23-mm/sup 2/GPS receiver with CPU-DSP-64 kRAM-256 kROM and a 27.2-mW
4.1-mm/sup 2/radio has been integrated in a 180-nm CMOS process. The SoC GPS …

A 2.7 mW, 90.3 dB DR Continuous-Time Quadrature Bandpass Sigma-Delta Modulator for GSM/EDGE Low-IF Receiver in 0.25 m CMOS

SB Kim, S Joeres, R Wunderlich… - IEEE Journal of Solid …, 2009 - ieeexplore.ieee.org
Quadrature bandpass SigmaDelta modulators based on polyphase filters are suited for
analog-to-digital conversion in GSM/EDGE low-IF receivers. This paper presents a …

[BOOK][B] LNA-ESD co-design for fully integrated CMOS wireless receivers

P Leroux, M Steyaert - 2006 - books.google.com
LNA-ESD Co-Design for Fully Integrated CMOS Wireless Receivers fits in the quest for
complete CMOS integration of wireless receiver front-ends. With a combined discussion of …

A 2.2-mW CMOS bandpass continuous-time multibit Δ-Σ ADC with 68 dB of dynamic range and 1-MHz bandwidth for wireless applications

MS Kappes - IEEE Journal of Solid-State Circuits, 2003 - ieeexplore.ieee.org
A delta-sigma (ΔΣ) analog-to-digital converter featuring 68-dB dynamic range and 64-dB
signal-to-noise ratio in a 1-MHz bandwidth centered at an intermediate frequency of 2 MHz …