We propose an open source cell library characterizer. Recently, free and open-sourced
silicon design communities are attracted by hobby designers, academies and industries …

In timing signoff for leading-edge SOCs, even few-picosecond timing violations will not only
increase design turnaround time, but also degrade design quality (eg, through power …

In static timing analysis, clock-to-q delays of flip-flops are considered as constants. Setup
times and hold times are characterized separately and also used as constants. The …

In this paper, the authors build a new modelling framework for the timing behaviour of a
flipflop by putting the clock-to-q delay into a nonlinear functional relationship with the …

Characterizing setup/hold times of latches and registers, which is a task crucial for achieving
timing closure of large digital designs, typically occupies months of computation in …

In advanced technology nodes, transistors and interconnects with shrinking physical
dimensions suffer large process variations during manufacturing and are prone to reliability …

Interdependent characterization of latch setup/hold times is a core component of techniques
for pessimism reduction via Setup/Hold Interdependence Aware Static Timing Analysis …

Clock skew scheduling is one of the essential steps to be carefully performed during the
design process. Two commonly used strategies for solving the task are the scheduling of …

In this work, we have analyzed the effects of variability, due to random dopant fluctuation
(RDF), on the timing characteristics of flip-flops for the future technology generations of 25 …

Interdependent setup-hold times are exploited during the design process to improve the
robustness of a circuit. Considering this interdependence only during static timing analysis …