Given the significance of placement in IC physical design, extensive research studies
performed over the last 50 years addressed numerous aspects of global and detailed …

Standard cell circuits consist of millions of standard cells, which have to be aligned overlap-
free to the rows of the chip. Placement of these circuits is done in consecutive steps. First, a …

We present a two-stage congestion-driven placement flow. First, during each refinement
stage of our multilevel global placement framework, we replace cells based on the …

In VLSI placement, legalization is an essential step where the overlaps between
gates/macros must be removed. In this paper, we introduce a history-based legalization …

Placement is one of the most important steps in the RTL-to-GDSII synthesis process as it
directly defines the interconnects. The rapid increase in IC design complexity and the …

In this paper, we propose a new linear programming based timing driven placement
framework for high performance designs. Our LP framework is mainly net-based, but it takes …

Improving routability during both global and detailed routing stage has become a critical
problem in modern VLSI design. In this work, we propose a placement framework that offers …

In a realistic design flow, circuit and system optimizations must interact with physical aspects
of the design. For example, improvements in timing and power may require the replacement …

This work proposes a novel latch placement methodology by computing optimized
placement templates with significantly lower local clock tree capacitance at a one-time cost …

Placement migration is the movement of cells within an existing placement to address a
variety of postplacement design-closure issues, such as timing, routing congestion, signal …