Current very-large-scale-integration (VLSI) technology allows the manufacture of large-area
integrated circuits with submicrometer feature sizes, enabling designs with several millions …

In this paper, we present a new low power test-per-clock BIST test pattern generator that
provides test vectors which can reduce the switching activity during test operation. The …

The defects that can occur when manufacturing VLSI ICs and the faults that can result are
described. Some commonly used restructuring techniques for avoiding defective …

We propose a novel approach for light field compression that incorporates disparity
compensation into 4D wavelet coding using disparity-compensated lifting. With this …

Topics related to the faults in SRAM-based field programmable gate arrays (FPGAs) have
been intensively studied in recent research studies. These topics include FPGA fault …

It has been recognized that the yield of fault-tolerant VLSI circuits depends on the size of the
fault clusters. Consequently, models for yield analysis have been proposed for large-area …

The discovery of a principle of synergistic fault tolerance is described, and it is shown
analytically why it occurs. The performance of its hardware implementation, in the form of a …

Several yield-enhancement techniques are proposed for the last two stages of VLSI design,
ie, topological/symbolic and physical layout synthesis. Our approach is based on …

The homogeneous structure of field programmable gate arrays (FPGAs) suggests that the
defect tolerance can be achieved by shifting the configuration data inside the FPGA. This …

(57) ABSTRACT A statistical method is described for reliability selection of dies on
Semiconductor wafers using critical wafer yield parameters. This is combined with other data …