Recent advances on multivalued logic gates: A materials perspective

SB Jo, J Kang, JH Cho - Advanced Science, 2021 - Wiley Online Library
The recent advancements in multivalued logic gates represent a rapid paradigm shift in
semiconductor technology toward a new era of hyper Moore's law. Particularly, the …

[HTML][HTML] Design implementations of ternary logic systems: A critical review

F Zahoor, RA Jaber, UB Isyaku, T Sharma, F Bashir… - Results in …, 2024 - Elsevier
In the electronics industry, binary devices have played a critical role since the development
of solid-state transistors. While binary technology associates devices' inherent ability to be …

CNTFET-based design of ternary logic gates and arithmetic circuits

S Lin, YB Kim, F Lombardi - IEEE transactions on …, 2009 - ieeexplore.ieee.org
This paper presents a novel design of ternary logic gates using carbon nanotube (CNT)
FETs (CNTFETs). Ternary logic is a promising alternative to the conventional binary logic …

Design of energy-efficient and robust ternary circuits for nanotechnology

MH Moaiyeri, A Doostaregan, K Navi - IET Circuits, Devices & Systems, 2011 - IET
Novel high-performance ternary circuits for nanotechnology are presented here. Each of
these carbon nanotube field-effect transistor (CNFET)-based circuits implements all the …

A logic synthesis methodology for low-power ternary logic circuits

S Kim, SY Lee, S Park, KR Kim… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
We propose a logic synthesis methodology with a novel low-power circuit structure for
ternary logic. The proposed methodology synthesizes a ternary function as a ternary logic …

Bi-objective elite differential evolution algorithm for multivalued logic networks

J Sun, S Gao, H Dai, J Cheng… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
In this paper, a novel algorithm called bi-objective elite differential evolution (BOEDE) is
proposed to optimize multivalued logic (MVL) networks. It is a multiobjective algorithm …

Tunnelling-based ternary metal–oxide–semiconductor technology

JW Jeong, YE Choi, WS Kim, JH Park, S Kim… - Nature …, 2019 - nature.com
The power density limits of complementary metal–oxide–semiconductor (CMOS) technology
could be overcome by moving from a binary to a ternary logic system. However, ternary …

Energy efficient design of unbalanced ternary logic gates and arithmetic circuits using CNTFET

T Khurshid, V Singh - AEU-International Journal of Electronics and …, 2023 - Elsevier
The emergence of multi-valued logic (MVL) is a substitute to binary logic approaches for
realizing high-information density logic systems and high-operating speed systems. In this …

Design and evaluation of multiple valued logic gates using pseudo N-type carbon nanotube FETs

J Liang, L Chen, J Han… - IEEE transactions on …, 2014 - ieeexplore.ieee.org
Multiple valued logic (MVL) circuits are particularly attractive for nanoscale implementation
as advantages in information density and operating speed can be harvested using emerging …

A novel CNTFET-based ternary logic gate design

S Lin, YB Kim, F Lombardi - 2009 52nd IEEE International …, 2009 - ieeexplore.ieee.org
This paper presents a novel design of ternary logic inverters using carbon nanotube FETs
(CNTFETs). Multiple-valued logic (MVL) circuits have attracted substantial interest due to the …