Next generation of exascale-class systems: Exanest project and the status of its interconnect and storage development
The ExaNeSt project started on December 2015 and is funded by EU H2020 research
framework (call H2020-FETHPC-2014, n. 671553) to study the adoption of low-cost, Linux …
framework (call H2020-FETHPC-2014, n. 671553) to study the adoption of low-cost, Linux …
[HTML][HTML] INRFlow: An interconnection networks research flow-level simulation framework
This paper presents INRFlow, a mature, frugal, flow-level simulation framework for modelling
large-scale networks and computing systems. INRFlow is designed to carry out performance …
large-scale networks and computing systems. INRFlow is designed to carry out performance …
Unilogic: A novel architecture for highly parallel reconfigurable systems
One of the main characteristics of High-performance Computing (HPC) applications is that
they become increasingly performance and power demanding, pushing HPC systems to …
they become increasingly performance and power demanding, pushing HPC systems to …
Cross-Chip Partial Reconfiguration for the Initialisation of Modular and Scalable Heterogeneous Systems
M Fuchs, H Krause, T Muscheid… - … on Nuclear Science, 2024 - ieeexplore.ieee.org
The almost unlimited possibilities to customize the logic in an FPGA are one of the main
reasons for the versatility of these devices. Partial reconfiguration exploits this capability …
reasons for the versatility of these devices. Partial reconfiguration exploits this capability …
Performance and energy footprint assessment of FPGAs and GPUs on HPC systems using astrophysics application
New challenges in Astronomy and Astrophysics (AA) are urging the need for many
exceptionally computationally intensive simulations.“Exascale”(and beyond) computational …
exceptionally computationally intensive simulations.“Exascale”(and beyond) computational …
[LIBRO][B] Resource Elastic Dynamic Stream Processing on FPGAs Exemplified on Database Acceleration
KN Manev - 2022 - search.proquest.com
While FPGAs are becoming mainstream in the deployment of datacenters and cloud
systems, they are mostly used as updatable ASICs. This thesis shows that it is feasible to …
systems, they are mostly used as updatable ASICs. This thesis shows that it is feasible to …
CHIPP: INAF pilot project for HTC, HPC and HPDA
CHIPP (Computing HTC in INAF Pilot Project) is an Italian project funded by the Italian
Institute for Astrophysics (INAF) and promoted by the ICT office of INAF. The main purpose of …
Institute for Astrophysics (INAF) and promoted by the ICT office of INAF. The main purpose of …
Optimized page fault handling during RDMA
Remote Direct Memory Access (RDMA) is widely used in High-Performance Computing
(HPC) while making inroads in datacenters and accelerators. State-of-the-art RDMA engines …
(HPC) while making inroads in datacenters and accelerators. State-of-the-art RDMA engines …
Virtualized multi-channel rdmawith software-defined scheduling
In HPC, low latency communication between remote processes is crucial to application
performance. InfiniBand networks can reduce the latency but require special and costly …
performance. InfiniBand networks can reduce the latency but require special and costly …
APEIRON: a Framework for High Level Programming of Dataflow Applications on Multi-FPGA Systems
High Energy Physics (HEP) Trigger and Data Acquisition systems (TDAQs) need ever
increasing throughput and real-time data analytics capabilities either to improve particle …
increasing throughput and real-time data analytics capabilities either to improve particle …