In the present day scenario, it has become a challenge to reduce static power dissipation as
we are progressing towards nanoscale domain. Interdie and intradie variations and varied …

The demand for low-power devices in today's world is increasing, and the reason behind
this is scaling CMOS technology. Due to scaling, the size of the chip decreases and the …

In this paper power and energy dissipation are reduced using transmission gate logic (TGL),
which are the challenging factors in the VLSI CMOS design. In order to get strong output …

On-chip SRAM array occupies a large area in the microprocessor ICs. This enforces the
technology to reach nano-scale domain. In this domain, minimizing the short channel effects …

The greatest challenge in VLSI design is reduction of power dissipation. Due to the scaling,
the leakage current of sub-threshold plays a key role in the total dissipation of power. This …

In this proposed work we are applying valuable power gating schemes to FinFET based
Schmitt trigger to enhance its performance by reducing the leakage current in standby mode …

This paper aims at reducing power and energy dissipation in Transmission Gate Logic (TGL)
Multiplexer CMOS circuits comprise of reducing the power supply voltages, power supply …

In this paper an embedded clock generation solution for low power sensor nodes is
presented. A design example of a Digitally Controlled Oscillator (DCO) is given and …

With CMOS process develo**, the Static Random Access Memory (SRAM) suffers
unavoidable degradation in terms of read and write stabilities. To optimise the memory with …

A conventional Full Adder using 28 transistors is presented here. In digital signal processors
and microprocessors, the Full Adder is not only important for addition based digital circuit …