Simba: Scaling deep-learning inference with multi-chip-module-based architecture

YS Shao, J Clemons, R Venkatesan, B Zimmer… - Proceedings of the …, 2019 - dl.acm.org
Package-level integration using multi-chip-modules (MCMs) is a promising approach for
building large-scale systems. Compared to a large monolithic die, an MCM combines many …

Nn-baton: Dnn workload orchestration and chiplet granularity exploration for multichip accelerators

Z Tan, H Cai, R Dong, K Ma - 2021 ACM/IEEE 48th Annual …, 2021 - ieeexplore.ieee.org
The revolution of machine learning poses an unprecedented demand for computation
resources, urging more transistors on a single monolithic chip, which is not sustainable in …

SPACX: Silicon photonics-based scalable chiplet accelerator for DNN inference

Y Li, A Louri, A Karanth - 2022 IEEE International Symposium …, 2022 - ieeexplore.ieee.org
In pursuit of higher inference accuracy, deep neural network (DNN) models have
significantly increased in complexity and size. To overcome the consequent computational …

A 1.17-pJ/b, 25-Gb/s/pin ground-referenced single-ended serial link for off-and on-package communication using a process-and temperature-adaptive voltage …

JW Poulton, JM Wilson, WJ Turner… - IEEE Journal of Solid …, 2018 - ieeexplore.ieee.org
This paper describes a short-reach serial link to connect chips mounted on the same
package or on neighboring packages on a printed circuit board (PCB). The link employs an …

PINE: photonic integrated networked energy efficient datacenters (ENLITENED program)

M Glick, NC Abrams, Q Cheng, MY Teh… - Journal of Optical …, 2020 - opg.optica.org
We review the motivation, goals, and achievements of the Photonic Integrated Networked
Energy efficient datacenter (PINE) project, which is part of the Advanced Research Projects …

A 1.02-pJ/b 20.83-Gb/s/wire USR transceiver using CNRZ-5 in 16-nm FinFET

A Tajalli, MB Parizi, DA Carnelli, C Cao… - IEEE Journal of Solid …, 2020 - ieeexplore.ieee.org
An energy-efficient (1.02 pJ/b) and high-speed (20.83 Gb/s/wire, 417 Gb/s/mm) link for ultra-
short reach (USR) applications (up to 6-dB channel loss at the Nyquist frequency of 12.5 …

Hardware-enabled artificial intelligence

WJ Dally, CT Gray, J Poulton, B Khailany… - … IEEE Symposium on …, 2018 - ieeexplore.ieee.org
The current resurgence of artificial intelligence is due to advances in deep learning. Systems
based on deep learning now exceed human capability in speech recognition [1], object …

A scalable multi-chip YOLO accelerator with a lightweight inter-chip adapter

J Kim, C Park, E Hyun, XT Nguyen… - 2024 IEEE International …, 2024 - ieeexplore.ieee.org
Multi-chip-module (MCM) technology offers a promising solution for designing large-scale
deep-learning inference systems while concurrently minimizing fabrication and design costs …

Simba: scaling deep-learning inference with chiplet-based architecture

YS Shao, J Cemons, R Venkatesan, B Zimmer… - Communications of the …, 2021 - dl.acm.org
Package-level integration using multi-chip-modules (MCMs) is a promising approach for
building large-scale systems. Compared to a large monolithic die, an MCM combines many …

Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects

WJ Turner, JW Poulton, JM Wilson… - 2018 IEEE Custom …, 2018 - ieeexplore.ieee.org
While high-speed single-ended signaling maximizes pin and wire utilization within on-and
off-chip serial links, problems associated with conventional signaling methods result in …