Customizing Cache Indexing Through Entropy Estimation

K Weston, A Johnson, V Janfaza… - 2024 57th IEEE/ACM …, 2024 - ieeexplore.ieee.org
Modern computers heavily rely on caches as one of the means to achieve higher
performance. As a result, cache management has been the topic of extensive research …

The Tag Filter Architecture: An energy-efficient cache and directory design

JJ Valls, A Ros, ME Gómez, J Sahuquillo - Journal of Parallel and …, 2017 - Elsevier
Power consumption in current high-performance chip multiprocessors (CMPs) has become
a major design concern that aggravates with the current trend of increasing the core count. A …

A self-reconfiguring cache architecture to improve control quality in cyber-physical systems

MS Haque, S Vasudevan, AS Nihar… - 2018 IEEE 21st …, 2018 - ieeexplore.ieee.org
Quality of control is a critical concern in Cyber-Physical Systems (CPS) which are comprised
of multiple intercommunicating control applications. Due to complex timing behaviour of …

Improving the performance and energy efficiency of gpgpu computing through integrated adaptive cache management

KY Kim, J Park, W Baek - IEEE Transactions on Parallel and …, 2018 - ieeexplore.ieee.org
Hardware caches are widely employed in GPGPUs to achieve higher performance and
energy efficiency. Incorporating hardware caches in GPGPUs, however, does not …

Parloom: a new low-power set-associative instruction cache architecture utilizing enhanced counting bloom filter and partial tags

S Rostami-Sani, M Valinataj… - Journal of Circuits …, 2019 - World Scientific
The cache system dissipates a significant amount of energy compared to the other memory
components. This will be intensified if a cache is designed with a set-associative structure to …

Reducing the second-level cache conflict misses using a set folding technique

A Shatnawi, M Alsaedeen - The Journal of Supercomputing, 2018 - Springer
The cache memory has a direct effect on the performance of a computer system. Instructions
and data are fetched from a fast cache instead of a slow memory to save hundreds of cycles …

Methods and apparatus for tracking instruction information stored in virtual sub-elements mapped to physical sub-elements of a given element

H Bouzguarrou, TE Lanois, G Bolbenes… - US Patent …, 2024 - Google Patents
Instruction information generation circuitry generates instruction information. Instruction
information storage circuitry comprises a plurality of elements having physical sub-elements …

[PDF][PDF] Improving the Performance and Energy Efficiency of GPGPU Computing through Adaptive Cache and Memory Management Techniques

KY Kim - 2020 - core.ac.uk
As the performance and energy efficiency requirement of GPGPUs have risen, memory
management techniques of GPGPUs have improved to meet the requirements by employing …

Evolution of application-specific cache map**s

N Ho, P Kaufmann, M Platzner - International Journal of Hybrid …, 2020 - content.iospress.com
Reconfigurable caches offer an intriguing opportunity to tailor cache behavior to applications
for better run-times and energy consumptions. While one may adapt structural cache …

[PDF][PDF] FPGA-based Reconfigurable Cache Map** Schemes: Design and Optimization

N Ho - 2018 - digital.ub.uni-paderborn.de
Traditional cache design uses a consolidated block of memory address bits to index a cache
set, equivalent to the use of modulo functions. While this module-based map** scheme is …