SIGFinger: A Subtle and Interactive GNN Fingerprinting Scheme via Spatial Structure Inference Perturbation
J Jia, R Li, C Wu, S Ma, L Wang… - IEEE Transactions on …, 2025 - ieeexplore.ieee.org
There have been significant improvements in intellectual property (IP) protection for deep
learning models trained on Euclidean data. However, the complex and irregular graph …
learning models trained on Euclidean data. However, the complex and irregular graph …
High-level synthesis-based watermarking using crypto-chain signature framework
A Sengupta, A Anshul - 2024 - IET
Designing reusable hardware intellectual property (IP) core (such as JPEG-CODEC) for
multimedia/electronic systems involves managing competing design goals like latency and …
multimedia/electronic systems involves managing competing design goals like latency and …
High-level synthesis-based watermarking using protein molecular biometric with facial biometric encryption
A Sengupta, A Anshul - 2024 - IET
This chapter discusses a watermarking-based hardware security methodology using an
encrypted protein molecular biometric signature to secure hardware intellectual property (IP) …
encrypted protein molecular biometric signature to secure hardware intellectual property (IP) …
High-level synthesis-based watermarking using multimodal biometric
A Sengupta, A Anshul - 2024 - IET
This chapter discusses hardware security methodologies for securing the transient fault-
secured hardware intellectual property (IP) designs using unified multimodal biometric and …
secured hardware intellectual property (IP) designs using unified multimodal biometric and …
HLS-based mathematical watermarks for hardware security and trust
A Sengupta, A Anshul - 2024 - IET
Ensuring security and trust within the global hardware design supply chain process is
paramount. Intellectual property (IP) piracy and false IP ownership assertion are two primary …
paramount. Intellectual property (IP) piracy and false IP ownership assertion are two primary …
HLS-based fingerprinting
A Sengupta, A Anshul - 2024 - IET
The utilization of hardware intellectual property (IP) cores within system-on-chip computing
architectures offers a distinct advantage by enhancing design productivity while reducing the …
architectures offers a distinct advantage by enhancing design productivity while reducing the …