Clocking analysis, implementation and measurement techniques for high-speed data links—A tutorial
The performance of high-speed wireline data links depend crucially on the quality and
precision of their clocking infrastructure. For future applications, such as microprocessor …
precision of their clocking infrastructure. For future applications, such as microprocessor …
A scalable 5–15 Gbps, 14–75 mW low-power I/O transceiver in 65 nm CMOS
We present a scalable low-power I/O transceiver in 65 nm CMOS, capable of 5-15 Gbps
operation over single-board and backplane FR4 channels with power efficiencies between …
operation over single-board and backplane FR4 channels with power efficiencies between …
10-Gbps, 5.3-mW optical transmitter and receiver circuits in 40-nm CMOS
FY Liu, D Patil, J Lexau, P Amberg… - IEEE journal of solid …, 2012 - ieeexplore.ieee.org
We describe transmitter and receiver circuits for a 10-Gbps single-ended optical link in a 40-
nm CMOS technology. The circuits are bonded using low-parasitic micro-solder bumps to …
nm CMOS technology. The circuits are bonded using low-parasitic micro-solder bumps to …
A scalable 0.128–1 Tb/s, 0.8–2.6 pJ/bit, 64-lane parallel I/O in 32-nm CMOS
M Mansuri, JE Jaussi, JT Kennedy… - IEEE Journal of solid …, 2013 - ieeexplore.ieee.org
A scalable 64-lane chip-to-chip I/O, with per-lane data rate of 2-16 Gb/s is demonstrated in
32-nm low-power CMOS technology. At maximum aggregate bandwidth of 1.024 Tb/s …
32-nm low-power CMOS technology. At maximum aggregate bandwidth of 1.024 Tb/s …
CMOS oscillators for clock distribution and injection-locked deskew
The distribution and alignment of high-frequency clocks across a wide bus of links is a
significant challenge in modern computing systems. A low power clock source is …
significant challenge in modern computing systems. A low power clock source is …
A 4710 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS
F O'Mahony, JE Jaussi, J Kennedy… - IEEE journal of solid …, 2010 - ieeexplore.ieee.org
A 47× 10 Gb/s chip-to-chip interface consuming 660 mW is demonstrated in 45 nm CMOS.
The circuitry and interconnect are co-designed to minimize power and area for a wide …
The circuitry and interconnect are co-designed to minimize power and area for a wide …
A 4–32 Gb/s bidirectional link with 3-tap FFE/6-tap DFE and collaborative CDR in 22 nm CMOS
This paper details the design of an 8-lane bidirectional link for both within-the-box and
external communications in 22 nm CMOS technology. A low profile connector with a high …
external communications in 22 nm CMOS technology. A low profile connector with a high …
Strong Injection Locking in Low- LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver
A general model for injection-locked LC oscillators (LC-ILOs) is presented that is valid for
any tank quality factor and injection strength. Important properties of an ILO such as lock …
any tank quality factor and injection strength. Important properties of an ILO such as lock …
7.4 Gb/s 6.8 mW source synchronous receiver in 65 nm CMOS
A high-frequency jitter tolerant receiver in 65 nm CMOS is presented. Jitter tolerance is
improved by tracking correlated jitter using a pulsed clock forwarded from the transmitter …
improved by tracking correlated jitter using a pulsed clock forwarded from the transmitter …
A 27Gb/s forwarded-clock I/O receiver using an injection-locked LC-DCO in 45nm CMOS
A 27Gb/s Forwarded-Clock I/O Receiver Using an Injection-Locked LC-DCO in 45nm CMOS
Page 1 452 • 2008 IEEE International Solid-State Circuits Conference ISSCC 2008 / SESSION …
Page 1 452 • 2008 IEEE International Solid-State Circuits Conference ISSCC 2008 / SESSION …