RTL to transistor level power modeling and estimation techniques for FPGA and ASIC: A survey

Y Nasser, J Lorandel, JC Prévotet… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
Power consumption constitutes a major challenge for electronics circuits. One possible way
to deal with this issue is to consider it very soon in the design process in order to explore …

[HTML][HTML] A dynamic reconfigurable architecture for hybrid spiking and convolutional fpga-based neural network designs

H Irmak, F Corradi, P Detterer, N Alachiotis… - Journal of Low Power …, 2021 - mdpi.com
This work presents a dynamically reconfigurable architecture for Neural Network (NN)
accelerators implemented in Field-Programmable Gate Array (FPGA) that can be applied in …

WALLAX: A memristor-based Gaussian random number generator

X Dong, A Amirsoleimani, MR Azghadi, R Genov - Neurocomputing, 2024 - Elsevier
Generating Gaussian random numbers is essential in many applications such as
cryptography, games, and computer simulations. Although software Gaussian Random …

Dyhard-dnn: Even more dnn acceleration with dynamic hardware reconfiguration

M Putic, S Venkataramani, S Eldridge… - Proceedings of the 55th …, 2018 - dl.acm.org
Deep Neural Networks (DNNs) have demonstrated their utility across a wide range of input
data types, usable across diverse computing substrates, from edge devices to datacenters …

Mindcrypt: The brain as a random number generator for soc-based brain-computer interfaces

G Eichler, B Seyoum, KL Chiu… - 2023 IEEE 41st …, 2023 - ieeexplore.ieee.org
True random number generation on resource-constrained devices is challenging due to
inherent hardware limitations; these limitations affect the ability to find a reliable source of …

Analysis of radiation-induced cross domain errors in TMR architectures on SRAM-based FPGAs

L Sterpone, L Boragno - … Symposium on On-Line Testing and …, 2017 - ieeexplore.ieee.org
SRAM-Based FPGAs represent a low-cost alternative to ASIC device thanks to their high
performance and design flexibility. In particular, for aerospace and avionics application …

An area efficient and low power consumption of run time digital system based on dynamic partial reconfiguration

R Saravana Ram, A Gopi Saminathan… - International Journal of …, 2020 - Springer
Digital signal processing besides multimedia applications needs plenty of data, real-time
processing capacity, and high computational power. Thus, adaptable architectures with run …

Network enabled partial reconfiguration for distributed FPGA edge acceleration

AR Bucknall, S Shreejith… - … conference on field …, 2019 - ieeexplore.ieee.org
Partial reconfiguration supports virtualisation of applications on FPGAs, enabling compute to
dynamically adapt to workloads in distributed infrastructure and datecenters. While the latter …

RISP: a reconfigurable in-storage processing framework with energy-awareness

X Song, T **e, W Pan - … Symposium on Cluster, Cloud and Grid …, 2018 - ieeexplore.ieee.org
Existing in-storage processing (ISP) techniques mainly focus on maximizing data processing
rate by always utilizing total storage data processing resources for all applications. We find …