Performance evaluation of application map** approaches for network-on-chip designs
Network-on-chip (NoC) is evolving as a better substitute for incorporating a large number of
cores on a single system-on-chip (SoC). The dependency on multi-core systems to …
cores on a single system-on-chip (SoC). The dependency on multi-core systems to …
Multi-threaded design of the applications has given a new dimension to the execution
concurrency. The Network-on-Chip (NoC) infrastructure has evolved as the communication …
concurrency. The Network-on-Chip (NoC) infrastructure has evolved as the communication …
Speichern Zitieren Zitiert von: 2 J Wang, Y Huang, M Ebrahimi, L Huang, Q Li… - Proceedings of the …, 2016 - dl.acm.org
Simulation is the most common approach to evaluate Network on Chip (NoC) designs and
many simulators at different abstraction levels have been developed so far. However …
many simulators at different abstraction levels have been developed so far. However …
A lifetime-aware map** algorithm to extend MTTF of networks-on-chip
Fast aging of components has become one of the major concerns in Systems-on-Chip with
further scaling of the submicron technology. This problem accelerates when combined with …
further scaling of the submicron technology. This problem accelerates when combined with …
Optimizing dynamic map** techniques for on-line NoC test
S Jiang, Q Wu, S Chen, J Wang… - 2018 23rd Asia and …, 2018 - ieeexplore.ieee.org
With the aggressive scaling of submicron technology, intermittent faults are becoming one of
the limiting factors in achieving a high reliability in Network-on-Chip (NoC). Increasing test …
the limiting factors in achieving a high reliability in Network-on-Chip (NoC). Increasing test …
Testing aware dynamic map** for path-centric network-on-chip test
With the aggressive scaling of submicron technology, intermittent faults are becoming one of
the limiting factors in achieving high reliability in Network-on-Chip (NoC). Increasing test …
the limiting factors in achieving high reliability in Network-on-Chip (NoC). Increasing test …
Scalable Run-time Task Map** on BNoC Topology Focusing on Energy-efficiency
The current work demonstrates a run-time application map** technique on the BNoC
network. Crucial properties of the BNoC design like low diameter and high path diversity …
network. Crucial properties of the BNoC design like low diameter and high path diversity …
Optimized map** algorithm to extend lifetime of both NoC and cores in many-core system
Fast aging of components has become one of the major concerns in Systems-on-Chip with
further scaling of the submicron technology, which is accelerated when the working …
further scaling of the submicron technology, which is accelerated when the working …
Towards Efficient Reuse of Software Programmable Streaming Coarse Grained Reconfigurable Architectures
EB Franco - 2021 - theses.hal.science
Coarse-Grained Reconfigurable Architectures (CGRA) are designed to deliver high
performance while drastically reducing the latency of the computing system. There are …
performance while drastically reducing the latency of the computing system. There are …
Research on robust design and optimization of embedded network electronic information system
P Yang, X Zhou, J Jia - Journal of Physics: Conference Series, 2020 - iopscience.iop.org
At present, in the process of designing and optimizing the robustness of embedded network
electronic information systems, it is found that many factors in the system have some …
electronic information systems, it is found that many factors in the system have some …