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A fast startup CMOS crystal oscillator using two-step injection
Fast startup crystal oscillators (XOs) are needed in heavily duty-cycled communication
systems for implementing aggressive dynamic power management schemes. This article …
systems for implementing aggressive dynamic power management schemes. This article …
A 6.75–8.25-GHz− 250-dB FoM rapid ON/OFF fractional-N injection-locked clock multiplier
A rapid ON/OFF LC-based fractional-N injection-locked clock multiplier (ILCM) is presented.
The proposed architecture extends the merits of ILCMs to fractional-N operation. It employs …
The proposed architecture extends the merits of ILCMs to fractional-N operation. It employs …
A 12-Gb/s 10-ns turn-on time rapid ON/OFF baud-rate DFE receiver in 65-nm CMOS
Rapid ON/OFF (ROO) operation helps scale power in accordance with link utilization. In this
article, we present a baud-rate ROO receiver that can turn on in just 10 ns (~ 120 TiI). Baud …
article, we present a baud-rate ROO receiver that can turn on in just 10 ns (~ 120 TiI). Baud …
All-digital PLL for Bluetooth low energy using 32.768-kHz reference clock and≤ 0.45-V supply
CC Li, MS Yuan, CC Liao, YT Lin… - IEEE Journal of Solid …, 2018 - ieeexplore.ieee.org
In this paper, we introduce an all-digital phase-locked loop (ADPLL) for Bluetooth low
energy (BLE) that eliminates the need for a crystal oscillator (XO) other than a 32.768-kHz …
energy (BLE) that eliminates the need for a crystal oscillator (XO) other than a 32.768-kHz …
A fast-lock all-digital clock generator for energy efficient chiplet-based systems
J **, S Kim, J Kim - IEEE Access, 2022 - ieeexplore.ieee.org
An all-digital clock frequency multiplier that achieves excellent locking time for an energy-
efficient chiplet-based system-on-chip (SoC) design is presented. The proposed architecture …
efficient chiplet-based system-on-chip (SoC) design is presented. The proposed architecture …
A 10-Gb/s/ch, 0.6-pj/bit/mm power scalable rapid-on/off transceiver for on-chip energy proportional interconnects
Modern multiprocessor system-on-chips employ network-on-chip (NoC) to efficiently connect
different components together. NoCs need global and local interconnects to deliver high on …
different components together. NoCs need global and local interconnects to deliver high on …
An iPWM line-coding-based wireline transceiver with clock-domain encoding for compensating up to 27-dB loss while operating at 0.5-to-0.9 V and 3-to-16 Gb/s in 65 …
A Ramachandran, Y Chun… - IEEE Journal of Solid …, 2020 - ieeexplore.ieee.org
This article presents a clock-domain-based integrated pulsewidth modulation (PWM)(iPWM)
line-coding scheme to enable equalization while operating at low supply voltages. While …
line-coding scheme to enable equalization while operating at low supply voltages. While …
Line coding techniques for channel equalization: Integrated pulse-width modulation and consecutive digit chop**
A Ramachandran, A Natarajan… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
This paper presents two new line-coding schemes, integrated pulse width modulation
(iPWM) and consecutive digit chop** (CDC) for equalizing lossy wireline channels with …
(iPWM) and consecutive digit chop** (CDC) for equalizing lossy wireline channels with …
Fast-Locking Burst-Mode Clock and Data Recovery for Parallel VCSEL-Based Optical Link Receivers
A burst-mode clock-and-data-recovery (CDR) system for a multi-channel vertical-cavity
surface-emitting laser (VCSEL)-based non-return-to-zero (NRZ) optical link's quarter-rate …
surface-emitting laser (VCSEL)-based non-return-to-zero (NRZ) optical link's quarter-rate …
Wireline communication: the backbone of data transfer
S Saxena - CSI Transactions on ICT, 2020 - Springer
This paper reviews the need of a high performance wireline communication in the
background of wirelessly connected billions of sensor nodes by 2020s. It compares the …
background of wirelessly connected billions of sensor nodes by 2020s. It compares the …