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Semiconductor device and manufacturing method thereof
CS Li, HC Huang, CW Liu - US Patent 9,905,467, 2018 - Google Patents
(57) ABSTRACT A semiconductor device includes a substrate, a first insulat ing structure, a
second insulating structure, at least one first active semiconductor fin, and at least one …
second insulating structure, at least one first active semiconductor fin, and at least one …
Stacked transistors with different channel widths
K Cheng, LA Clevenger, BS Pranatharthiharan… - US Patent …, 2019 - Google Patents
A semiconductor device includes a first gate stack arranged about a first nanowire and a
second nanowire, the first nanowire is arranged above a second nanowire, the first …
second nanowire, the first nanowire is arranged above a second nanowire, the first …
Methods for fabricating integrated circuits using flowable chemical vapor deposition techniques with low-temperature thermal annealing
2014/0306317 Al 10/2014 Licausi 2014/0353795 Al 12/2014 Tong et al. 2017/0053798 Al*
2/2017 Wang................ HO1L 21/02348* cited by examiner Primary Examiner—John P Dulka …
2/2017 Wang................ HO1L 21/02348* cited by examiner Primary Examiner—John P Dulka …
FinFET having locally higher fin-to-fin pitch
The disclosed technology generally relates to semiconductor devices, and more particularly
to FinFET transistors. In one aspect, at least three fins are arranged to extend in parallel in a …
to FinFET transistors. In one aspect, at least three fins are arranged to extend in parallel in a …
Semiconductor device and a method for fabricating the same
YD Chiou, C Janet, JYD Yeh - US Patent 10,134,872, 2018 - Google Patents
In a method of manufacturing a semiconductor device, a dummy gate structure is formed
over a substrate. A source/drain region is formed. A first insulating layer is formed over the …
over a substrate. A source/drain region is formed. A first insulating layer is formed over the …
FinFET having controlled dielectric region height
BACKGROUND The present disclosure relates in general to semiconductor devices and
their manufacture, and more specifically to con trolling the height of a dielectric region of a …
their manufacture, and more specifically to con trolling the height of a dielectric region of a …
Semiconductor device including active fin
S Kim, DH Cha, SS Paak - US Patent 10,199,499, 2019 - Google Patents
(57) ABSTRACT A semiconductor device includes first through fourth active fins, which
extend alongside one another in a first direction; and a field insulating film that covers lower …
extend alongside one another in a first direction; and a field insulating film that covers lower …
Uniform dielectric recess depth during fin reveal
(57) ABSTRACT A method for providing a uniform recess depth between different fin gap
sizes includes depositing a dielectric mate rial between fins on a Substrate. Etchlag is tuned …
sizes includes depositing a dielectric mate rial between fins on a Substrate. Etchlag is tuned …
Fin type field effect transistors with different pitches and substantially uniform fin reveal
Z Bi, K Cheng, TS Devarajan… - US Patent …, 2017 - Google Patents
(57) ABSTRACT A semiconductor device that includes a first plurality offin structures in a first
device region and a second plurality of fin structures in a second device region. The first …
device region and a second plurality of fin structures in a second device region. The first …
Homogeneous densification of fill layers for controlled reveal of vertical fins
In accordance with an embodiment of the present invention, a method of forming a densified
fill layer is provided. The method includes forming a pair of adjacent vertical fins on a …
fill layer is provided. The method includes forming a pair of adjacent vertical fins on a …