Specification and verification of side-channel security for open-source processors via leakage contracts

Z Wang, G Mohr, K von Gleissenthall… - Proceedings of the …, 2023 - dl.acm.org
Leakage contracts have recently been proposed as a new security abstraction at the
Instruction Set Architecture (ISA) level. Leakage contracts aim to capture the information that …

Testing side-channel security of cryptographic implementations against future microarchitectures

G Barthe, M Böhme, S Cauligi… - Proceedings of the …, 2024 - dl.acm.org
How will future microarchitectures impact the security of existing cryptographic
implementations? As we cannot keep reducing the size of transistors, chip vendors have …

Synthesizing hardware-software leakage contracts for RISC-V open-source processors

G Mohr, M Guarnieri, J Reineke - 2024 Design, Automation & …, 2024 - ieeexplore.ieee.org
Microarchitectural attacks compromise security by exploiting software-visible artifacts of
microarchitectural optimizations such as caches and speculative execution. Defending …

This is how you lose the transient execution war

A Randal - arxiv preprint arxiv:2309.03376, 2023 - arxiv.org
A new class of vulnerabilities related to speculative and out-of-order execution, fault-
injection, and microarchitectural side channels rose to attention in 2018. The techniques …

SCAFinder: Formal Verification of Cache Fine-Grained Features for Side Channel Detection

S Zhang, H Wang, P Qiu, Y Lyu… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
Recent research has unveiled numerous cache-timing side-channel attacks exploiting the
side effects of fine-grained cache features, such as coherence protocol and prefetch, among …

[PDF][PDF] Phantom Trails: Practical Pre-Silicon Discovery of Transient Data Leaks

A de Faveri Tron, R Isemann, H Ragab… - USENIX …, 2025 - download.vusec.net
Transient execution vulnerabilities have affected CPUs for the better part of the decade, yet,
we are still missing methods to efficiently uncover them at the design stage. Existing …

GraphFuzz: Accelerating Hardware Testing with Graph Models

R Saravanan, S Kasarapu, SMP Dinakarrao - arxiv preprint arxiv …, 2024 - arxiv.org
The increasing complexity of modern processor and IP designs presents significant
challenges in identifying and mitigating hardware flaws early in the IC design cycle …

BETA: Automated Black-box Exploration for Timing Attacks in Processors

C Chen, J Cui, J Zhang - arxiv preprint arxiv:2410.16648, 2024 - arxiv.org
Modern processor advancements have introduced security risks, particularly in the form of
microarchitectural timing attacks. High-profile attacks such as Meltdown and Spectre have …

Transient execution vulnerabilities in the security context of server hardware

A Randal - 2023 - cl.cam.ac.uk
Many mitigations have been proposed and implemented for many variants of the transient
execution vulnerabilities, and while the Meltdown-type exception-based transient execution …

[PDF][PDF] Fuzzing for Discovering Bugs and Side Channels in Processors

Fuzzing for Discovering Bugs and Side Channels in Processors Page 1 Department of
Electrical and Computer Engineering Fuzzing for Discovering Bugs and Side Channels in …