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An overview of through-silicon-via technology and manufacturing challenges
The idea of using through-silicon-via (TSV) technology has been around for many years.
However, this technology has only recently been introduced into high volume …
However, this technology has only recently been introduced into high volume …
LCHR-TSV: Novel low cost and highly repairable honeycomb-based TSV redundancy architecture for clustered faults
Due to the winding level of the thinned wafers and the surface roughness of silicon dies, the
quality of through-silicon vias (TSVs) varies during the fabrication and bonding process. If …
quality of through-silicon vias (TSVs) varies during the fabrication and bonding process. If …
Design-space exploration and optimization of an energy-efficient and reliable 3-D small-world network-on-chip
A 3-D network-on-chip (NoC) enables the design of high performance and low power many-
core chips. Existing 3-D NoCs are inadequate for meeting the ever-increasing performance …
core chips. Existing 3-D NoCs are inadequate for meeting the ever-increasing performance …
TSV open defects in 3D integrated circuits: Characterization, test, and optimal spare allocation
Three-dimensional integration based on die/wafer stacking and through-silicon-vias (TSVs)
promises to overcome interconnect bottlenecks for nanoscale integrated circuits (ICs) …
promises to overcome interconnect bottlenecks for nanoscale integrated circuits (ICs) …
A novel TDMA-based fault tolerance technique for the TSVs in 3D-ICs using honeycomb topology
T Ni, Z Yang, H Chang, X Zhang, L Lu… - IEEE transactions on …, 2020 - ieeexplore.ieee.org
Through-silicon-vias (TSVs) are prone to defects during the manufacturing process, which
pose yield challenges for three dimensional integrated circuits (3D-ICs). The area per TSV is …
pose yield challenges for three dimensional integrated circuits (3D-ICs). The area per TSV is …
On effective through-silicon via repair for 3-D-stacked ICs
3-D-stacked integrated circuits (ICs) that employ through-silicon vias (TSVs) to connect
multiple dies vertically have gained wide-spread interest in the semiconductor industry. In …
multiple dies vertically have gained wide-spread interest in the semiconductor industry. In …
Yield enhancement for 3D-stacked ICs: Recent advances and challenges
Three-dimensional (3D) integrated circuits (ICs) that stack multiple dies vertically using
through-silicon vias (TSVs) have gained wide interests of the semiconductor industry. The …
through-silicon vias (TSVs) have gained wide interests of the semiconductor industry. The …
Security and vulnerability implications of 3D ICs
Physical limit of transistor miniaturization has driven chip design into the third dimension. 3D
integration technology emerges as a viable option to improve chip performance and …
integration technology emerges as a viable option to improve chip performance and …
TSV defects and TSV-induced circuit failures: The third dimension in test and design-for-test
3D integrated circuits (3D ICs) based on through-silicon vias (TSVs) have emerged as a
promising solution for overcoming interconnect and power bottlenecks in IC design …
promising solution for overcoming interconnect and power bottlenecks in IC design …
Architecture of ring-based redundant TSV for clustered faults
WH Lo, K Chi, TT Hwang - IEEE Transactions on Very Large …, 2016 - ieeexplore.ieee.org
Three-dimensional integrated circuits (3-D-ICs) that employ the through-silicon vias (TSVs)
vertically stacking multiple dies provide many benefits, such as high density, high …
vertically stacking multiple dies provide many benefits, such as high density, high …