A closer look at spatiotemporal convolutions for action recognition

D Tran, H Wang, L Torresani, J Ray… - Proceedings of the …, 2018 - openaccess.thecvf.com
In this paper we discuss several forms of spatiotemporal convolutions for video analysis and
study their effects on action recognition. Our motivation stems from the observation that 2D …

A detailed and flexible cycle-accurate network-on-chip simulator

N Jiang, DU Becker, G Michelogiannakis… - … analysis of systems …, 2013 - ieeexplore.ieee.org
Network-on-Chips (NoCs) are becoming integral parts of modern microprocessors as the
number of cores and modules integrated on a single chip continues to increase. Research …

Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives

R Marculescu, UY Ogras, LS Peh… - … on computer-aided …, 2008 - ieeexplore.ieee.org
To alleviate the complex communication problems that arise as the number of on-chip
components increases, network-on-chip (NoC) architectures have been recently proposed …

Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems

E Ebrahimi, CJ Lee, O Mutlu, YN Patt - ACM Sigplan Notices, 2010 - dl.acm.org
Cores in a chip-multiprocessor (CMP) system share multiple hardware resources in the
memory subsystem. If resource sharing is unfair, some applications can be delayed …

Kilo-NOC: a heterogeneous network-on-chip architecture for scalability and service guarantees

B Grot, J Hestness, SW Keckler, O Mutlu - ACM SIGARCH computer …, 2011 - dl.acm.org
Today's chip-level multiprocessors (CMPs) feature up to a hundred discrete cores, and with
increasing levels of integration, CMPs with hundreds of cores, cache tiles, and specialized …

Aergia: Exploiting packet latency slack in on-chip networks

R Das, O Mutlu, T Moscibroda, CR Das - ACM SIGARCH computer …, 2010 - dl.acm.org
Traditional Network-on-Chips (NoCs) employ simple arbitration strategies, such as round-
robin or oldest-first, to decide which packets should be prioritized in the network. This is …

Application-aware prioritization mechanisms for on-chip networks

R Das, O Mutlu, T Moscibroda, CR Das - … of the 42nd annual IEEE/ACM …, 2009 - dl.acm.org
Network-on-Chips (NoCs) are likely to become a critical shared resource in future many-
core processors. The challenge is to develop policies and mechanisms that enable multiple …

SurfNoC: A low latency and provably non-interfering approach to secure networks-on-chip

HMG Wassel, Y Gao, JK Oberg, T Huffmire… - ACM SIGARCH …, 2013 - dl.acm.org
As multicore processors find increasing adoption in domains such as aerospace and
medical devices where failures have the potential to be catastrophic, strong performance …

Throughput-effective on-chip networks for manycore accelerators

A Bakhoda, J Kim, TM Aamodt - 2010 43rd Annual IEEE/ACM …, 2010 - ieeexplore.ieee.org
As the number of cores and threads in manycore compute accelerators such as Graphics
Processing Units (GPU) increases, so does the importance of on-chip interconnection …

[KSIĄŻKA][B] Efficient microarchitecture for network-on-chip routers

DU Becker - 2012 - search.proquest.com
Continuing advances in semiconductor technology, coupled with an increasing concern for
energy efficiency, have led to an industry-wide shift in focus towards modular designs that …