Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode

K Hepola, J Multanen… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
Transport triggered architectures (TTAs) follow the static programming model of very long
instruction word (VLIW) processors but expose additional information of the processor …

LiCryptor: High-Speed and Compact Multi-Grained Reconfigurable Accelerator for Lightweight Cryptography

HL Pham, VTD Le, TH Vu… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
Emerging modern internet-of-things (IoT) systems require hardware development to support
multiple 8/32/64-bit lightweight cryptographic (LWC) algorithms with high speed and energy …

LiteAIR5: a system-level framework for the design and modeling of AI-extended RISC-V cores

Y Gao, S Mosanu, MN Sakib, V Verma… - 2023 IEEE 36th …, 2023 - ieeexplore.ieee.org
The rapid evolution of machine learning applications along with the exponential growth in
the Internet of Things (IoT) has driven a surge in demand for high-performance and energy …

ASIPAMPIUM: An efficient ASIP generator for low power applications

A Engroff, M Romanssini, L Compassi-Severo… - Electronics, 2023 - mdpi.com
The adoption of customized ASIPs (Application Specific Instruction Set Processors) in
embedded circuits is an important alternative for optimizing power consumption, silicon …

Extending clang/LLVM with custom instructions using TableGen–an experience report

J Schlamelcher, T Goodfellow… - MBMV 2024; 27 …, 2024 - ieeexplore.ieee.org
The extensibility of the RISC-V ISA by adding instructions allows for the rapid creation of
custom processor cores. For that reason, it must be assured that the software tooling for this …

Bitstream Database-Driven FPGA Programming Flow Based on Standard OpenCL

T Leppänen, L Leppänen, J Multanen… - … Transactions on Very …, 2024 - ieeexplore.ieee.org
Field-programmable gate array (FPGA) vendors provide high-level synthesis (HLS)
compilers with accompanying OpenCL runtimes to enable easier use of their devices by non …

Seal5: Semi-Automated LLVM Support for RISC-V ISA Extensions Including Autovectorization

P Van Kempen, M Salmen… - 2024 27th Euromicro …, 2024 - ieeexplore.ieee.org
The RISC-V instruction set architecture (ISA) is popular for its extensibility, allowing easy
integration of custom vendor-defined instructions tailored to specific applications. However …

Application Specific Instruction-set Processors for Massive MIMO Systems

M Attari - 2024 - portal.research.lu.se
This is an undeniable fact now that wireless systems pervade all aspects of our lives. These
systems are evolving at a rapid clip, connecting more people and devices every single day …

Dual-IS: Instruction set modality for efficient instruction level parallelism

K Hepola, J Multanen, P Jääskeläinen - International Conference on …, 2022 - Springer
Exploiting instruction level parallelism (ILP) is a widely used method for increasing
performance of processors. While traditional very long instruction word (VLIW) processors …

Fully Automatic Compiler Retargeting and CV-X-IF Hardware Interface Generation for RISC-V Custom Instructions

K Hepola, TR Arachchige, J Multanen… - 2024 IEEE Nordic …, 2024 - ieeexplore.ieee.org
Application-specific instruction-set processors (ASIPs) can yield significantly better
performance and energy efficiency results compared to general-purpose processors, while …