Proactive deadlock prevention based on traffic classification sub-graphs for triplet-based NoC TriBA-cNoC

K Soliman, S Feng, R Shengqiang, C Li - Microprocessors and …, 2024 - Elsevier
Network topology and routing algorithms stand as pivotal decision points that profoundly
impact the performance of Network-on-Chip (NoC) systems. As core counts rise, so does the …

[HTML][HTML] A secure SoC architecture design with dual DMA controllers

W Wang, C He, J Shi - AIP Advances, 2024 - pubs.aip.org
With the continuous advancement of System-on-Chip (SoC) technologies, the burgeoning
data volumes emphasize the paramount importance of safeguarding data security and …

[HTML][HTML] Implementation of Motion Detection Methods on Embedded Systems: A Performance Comparison

K Sehairi, F Chouireb - International Journal of Technology, 2023 - ijtech.eng.ui.ac.id
Recently, deploying machine learning methods and deep learning models to create an
artificial intelligence system has gained huge interest. Several technologies, such as …

High Power Density Buck Boost DC/DC Converter Using SIC MOSFET

Z Rana, R Meng, K Ali, R Haseeb - Journal of Physics …, 2024 - iopscience.iop.org
High power density is an advance in power electronics. Third generation wide-bandgap
semiconductor devices (WBG SICs) offer significantly improved performance compared to …

[HTML][HTML] DMA controller design based on SHA-1 dual channel improvement algorithm

W Wang, C He, JQ Shi - AIP Advances, 2023 - pubs.aip.org
In order to make direct memory access (DMA) high-speed transmission while ensuring the
security and integrity of data, the traditional Secure Hash Algorithm (SHA) is improved from …

[PDF][PDF] An approach towards improvement of contiguous memory allocation linux kernel: A review

AS Suryavanshi, S Sharma - Indonesian Journal of Electrical …, 2022 - academia.edu
(DMA) and reserved static memory at boot time. But these solutions have its own drawbacks
such as, IOMMU requires hardware. However, the configuration of additional hardware's …

[PDF][PDF] Security analysis of hybrid Intel CPU/FPGA platforms using IOMMUs against I/O attacks

C Peglow, T Eisenbarth - Master's thesis. University of Lübeck, 2020 - its.uni-luebeck.de
This master thesis reviews the security of state-of-the-art hybrid platforms consisting of Intel
Xeon CPUs and Field Programmable Gate Arrays (FPGAs). These are now increasingly …

[PDF][PDF] Improving graphics processing unit performance based on neural network direct memory access controller

S Kumar, SB Neelappa… - Indonesian Journal of …, 2023 - pdfs.semanticscholar.org
In this paper proposes the design and implementation of the back-propagation algorithm
(BPA) based neural network direct memory access (DMA) controller for use of multimedia …

A Smart Memory Controller for System on Chip‐Based Devices

MA Ahmed, J Aloufi - Journal of Nanomaterials, 2022 - Wiley Online Library
This research paper deals with a system‐on‐chip (SoC) architecture design where multiple
processors are inbuilt with other blocks of memory and control logic developed by …

Implementation of Direct Memory Access for Parallel Processing

C Arun, A Gopinath, A Hanumanthaiah… - 2020 4th International …, 2020 - ieeexplore.ieee.org
There has been an ever growing complexity in design and development of Embedded
Systems for various applications. The applications like disaster management in a remote …