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Addressing transient and permanent faults in NoC with efficient fault-tolerant deflection router
Continuing decrease in the feature size of integrated circuits leads to increases in
susceptibility to transient and permanent faults. This paper proposes a fault-tolerant solution …
susceptibility to transient and permanent faults. This paper proposes a fault-tolerant solution …
A reconfigurable fault-tolerant deflection routing algorithm based on reinforcement learning for network-on-chip
We propose a reconfigurable fault-tolerant deflection routing algorithm (FTDR) based on
reinforcement learning for NoC. The algorithm reconfigures the routing table through a kind …
reinforcement learning for NoC. The algorithm reconfigures the routing table through a kind …
A survey of memory architecture for 3D chip multi-processors
Abstract 3D chip multi-processors (3D CMPs) combine the advantages of 3D integration and
the parallelism of CMPs, which are emerging as active research topics in VLSI and multi …
the parallelism of CMPs, which are emerging as active research topics in VLSI and multi …
Ultra-low-latency lightweight DMA for tightly coupled multi-core clusters
The evolution of multi-and many-core platforms is rapidly increasing the available on-chip
computational capabilities of embedded computing devices, while memory access is …
computational capabilities of embedded computing devices, while memory access is …
DMNI: A specialized network interface for NoC-based MPSoCs
Current proposals of NoC-based MPSoC adopt an NI (Network Interface) interconnected to
a DMA (Direct Memory Access) module to enable the communication between processors …
a DMA (Direct Memory Access) module to enable the communication between processors …
Software controlled memories for scalable many-core architectures
Technology scaling along with the ever evolving demand for media-rich software stacks
have motivated the need for many-core platforms. With the increase in compute power and …
have motivated the need for many-core platforms. With the increase in compute power and …
MMNoC: Embedding memory management units into network-on-chip for lightweight embedded systems
With the advent of the Internet-of-Things (IoT) era, the demand for lightweight embedded
systems is rapidly increasing. So far, ultra-low power (ULP) processors have been leading …
systems is rapidly increasing. So far, ultra-low power (ULP) processors have been leading …
NoC based distributed partitionable memory system for a coarse grain reconfigurable architecture
This paper presents a Network-on-Chip based distributed partitionable memory system for a
Dynamic Reconfigurable Resource Array (DRRA). The main purpose of this design is to …
Dynamic Reconfigurable Resource Array (DRRA). The main purpose of this design is to …
Energy-aware fault-tolerant network-on-chips for addressing multiple traffic classes
This paper presents an energy efficient architecture to provide on-demand fault tolerance to
multiple traffic classes, running simultaneously on single network on chip (NoC) platform …
multiple traffic classes, running simultaneously on single network on chip (NoC) platform …
A divide and conquer based distributed run-time map** methodology for many-core platforms
Real-time applications are raising the challenge of unpredictability. This is an extremely
difficult problem in the context of modern, dynamic, multiprocessor platforms which, while …
difficult problem in the context of modern, dynamic, multiprocessor platforms which, while …