Addressing transient and permanent faults in NoC with efficient fault-tolerant deflection router

C Feng, Z Lu, A Jantsch, M Zhang… - IEEE Transactions on …, 2012 - ieeexplore.ieee.org
Continuing decrease in the feature size of integrated circuits leads to increases in
susceptibility to transient and permanent faults. This paper proposes a fault-tolerant solution …

A reconfigurable fault-tolerant deflection routing algorithm based on reinforcement learning for network-on-chip

C Feng, Z Lu, A Jantsch, J Li, M Zhang - Proceedings of the Third …, 2010 - dl.acm.org
We propose a reconfigurable fault-tolerant deflection routing algorithm (FTDR) based on
reinforcement learning for NoC. The algorithm reconfigures the routing table through a kind …

A survey of memory architecture for 3D chip multi-processors

Y Zhang, L Li, Z Lu, A Jantsch, M Gao, H Pan… - Microprocessors and …, 2014 - Elsevier
Abstract 3D chip multi-processors (3D CMPs) combine the advantages of 3D integration and
the parallelism of CMPs, which are emerging as active research topics in VLSI and multi …

Ultra-low-latency lightweight DMA for tightly coupled multi-core clusters

D Rossi, I Loi, G Haugou, L Benini - … of the 11th ACM Conference on …, 2014 - dl.acm.org
The evolution of multi-and many-core platforms is rapidly increasing the available on-chip
computational capabilities of embedded computing devices, while memory access is …

DMNI: A specialized network interface for NoC-based MPSoCs

M Ruaro, FB Lazzarotto, CA Marcon… - … Symposium on Circuits …, 2016 - ieeexplore.ieee.org
Current proposals of NoC-based MPSoC adopt an NI (Network Interface) interconnected to
a DMA (Direct Memory Access) module to enable the communication between processors …

Software controlled memories for scalable many-core architectures

LAD Bathen, ND Dutt - … and Real-Time Computing Systems and …, 2012 - ieeexplore.ieee.org
Technology scaling along with the ever evolving demand for media-rich software stacks
have motivated the need for many-core platforms. With the increase in compute power and …

MMNoC: Embedding memory management units into network-on-chip for lightweight embedded systems

H Jang, K Han, S Lee, JJ Lee, W Lee - IEEE Access, 2019 - ieeexplore.ieee.org
With the advent of the Internet-of-Things (IoT) era, the demand for lightweight embedded
systems is rapidly increasing. So far, ultra-low power (ULP) processors have been leading …

NoC based distributed partitionable memory system for a coarse grain reconfigurable architecture

MA Tajammul, MA Shami, A Hemani… - 2011 24th Internatioal …, 2011 - ieeexplore.ieee.org
This paper presents a Network-on-Chip based distributed partitionable memory system for a
Dynamic Reconfigurable Resource Array (DRRA). The main purpose of this design is to …

Energy-aware fault-tolerant network-on-chips for addressing multiple traffic classes

SMAH Jafri, L Guang, A Hemani, K Paul… - Microprocessors and …, 2013 - Elsevier
This paper presents an energy efficient architecture to provide on-demand fault tolerance to
multiple traffic classes, running simultaneously on single network on chip (NoC) platform …

A divide and conquer based distributed run-time map** methodology for many-core platforms

I Anagnostopoulos, A Bartzas… - … , Automation & Test …, 2012 - ieeexplore.ieee.org
Real-time applications are raising the challenge of unpredictability. This is an extremely
difficult problem in the context of modern, dynamic, multiprocessor platforms which, while …