This paper aims to explore diverse landscape of Phase Locked Loops (PLLs), offering a
comprehensive categorization and in-depth analysis of their underlying working principles …

In a classical PLL, the phase detector (PD) and charge pump (CP) noise is multiplied by N 2,
when referred to the VCO output, due to the divide-by-N in the feedback path. It often …

This paper describes a fractional-N subsampling PLL in 28 nm CMOS. Fractional phase lock
is made possible with almost no penalty in phase noise performance thanks to the use of a …

This article presents a low-voltage (LV) sub-sampling phase-locked loop (LVSSPLL). The
architecture of hybrid dual-path loop-based SSPLL is proposed to mitigate the issue of …

This article proposes a fractional-N digital phase-locked loop (DPLL) that achieves a 265-
μW ultra-lowpower operation. The proposed switching feedback can seamlessly change the …

This paper introduces a quadrature fractional-N cascaded frequency synthesizer and its
phase noise analysis, optimization, and design for future 5G wireless transceivers. The …

Dividerless synthesizers such as sub-sampling phase-locked loops (PLLs) and injection-
locked clock multipliers have demonstrated some of the lowest jitters for a given power …

This article presents a low-jitter, low-fractional spur fractional-subsampling phase-locked
loop (SSPLL) that generates an output frequency,, that ranges from 12.8 to 15.0 GHz …

We present an analog subsampling PLL based on a digital-to-time converter (DTC), which
operates with almost no performance gap (176/198 fs RMS jitter) between the integer and …

This work presents a fully integrated 140-GHz transmitter (TX) achieving a data rate of 160
Gb/s with~ 1-pJ/b efficiency in the 22-nm Intel FinFET technology. The TX leverages a …