As the traditional more Moore approach is slowing down, due to the increase in
development costs and logic complexity, 3D technologies are enabling complex More than …

Imec's view on the key reliability issues related to 3D integration is discussed. First, through-
silicon via (TSV) reliability concerns linked to thermo-mechanical stresses induced in copper …

This paper demonstrates the fabrication of a reliable 0.7 μm diameter and 5μm deep (0.7
x5μm) via-last module, fitting a 1.4 μm TSV pitch. Enabling sub-micron TSV diameters …

We report laser-based fault isolation methodologies for the localization of open and short
failures in 1× 5 μm via-last through-silicon via (TSV) structures for 3-D system-on-chip (SoC) …

An advanced Via-Middle TSV metallization scheme is presented, featuring a high conformal
ALD oxide liner, a thermal ALD WN barrier, an electroless NiB platable seed and a high …

This paper discusses the key technological aspects of via-middle Cu through-silicon vias
(TSVs). The 3-D integration concept and the wafer front and backside process technology for …

The electrical reliability of 1 µm pitch wafer-to-wafer (W2W) Cu/SiCN hybrid bonding
interface is evaluated. Breakdown voltage distributions of the W2W hybrid stack were …

Wafer-on-wafer-on-wafer integration, consisting of three device wafers, is a key concept that
accelerates the evolution of stacked devices. We have successfully developed Wafer-On …

A 1× 5μm via-last TSV module is presented, co** with the reliability challenges imposed
when exposing the metal landing pad during the liner opening etch at the TSV bottom. Two …

The lifetime reliability of 3D-IC is limited due to defects, thermal issues and aging of Through-
silicon-via (TSV). The state-of-the-art methodologies for enhancing reliability are based on …