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Margin elimination through timing error detection in a near-threshold enabled 32-bit microcontroller in 40-nm CMOS
This paper presents a near-threshold operating voltage timing error detecting 32-bit
microcontroller system. The lightweight in situ error detection and correction technique uses …
microcontroller system. The lightweight in situ error detection and correction technique uses …
A sub 10 pJ/cycle over a 2 to 200 MHz performance range RISC-V microprocessor in 28 nm FDSOI
R Uytterhoeven, W Dehaene - ESSCIRC 2018-IEEE 44th …, 2018 - ieeexplore.ieee.org
This work presents a near-threshold microprocessor implementation that aims for ultra-high
energy-efficiency, while providing MHz performances over a 100x frequency range. This …
energy-efficiency, while providing MHz performances over a 100x frequency range. This …
iEDCL: Streamlined, False-Error-Free Error Detection and Correction Scheme in a Near-Threshold Enabled 32-bit Processor
R Yu, Z Li, X Deng, Z Wang, W Jia… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
This article presents internal error detection, correction, and latching (iEDCL), a designer-
friendly, fully functional error detection and correction (EDAC) approach tailored for energy …
friendly, fully functional error detection and correction (EDAC) approach tailored for energy …
[KNIHA][B] Efficient Design of Variation-Resilient Ultra-Low Energy Digital Processors
H Reyserhove, W Dehaene - 2019 - books.google.com
This book enables readers to achieve ultra-low energy digital system performance. The
author's main focus is the energy consumption of microcontroller architectures in digital …
author's main focus is the energy consumption of microcontroller architectures in digital …
Design and Analysis of Leakage-Induced False Error Tolerant Error Detecting Latch for Sub/Near-Threshold Applications
P Sharma, BP Das - IEEE Transactions on Device and Materials …, 2020 - ieeexplore.ieee.org
The digital designs operating in sub/near-threshold region are susceptible to timing errors
due to the extreme impact of process, voltage, and temperature (PVT) variations. This paper …
due to the extreme impact of process, voltage, and temperature (PVT) variations. This paper …
Design margin elimination through robust timing error detection at ultra-low voltage
This paper discusses a timing error masking-aware ARM Cortex M0 microcontroller system.
Through in-path timing error detection, operation at the point-of-first-failure is possible …
Through in-path timing error detection, operation at the point-of-first-failure is possible …
Efficient VLSI Design Flow
The efficient design flow presented in this chapter is a crucial aspect of this work. Full custom
design approaches succeed in enabling ultra-low energy operation, but are too time …
design approaches succeed in enabling ultra-low energy operation, but are too time …
Energy-Efficient Processors: Challenges and Solutions
This work tries to combine the described challenges that energy-efficient microcontrollers
face in sub-micron CMOS technologies. An ultra-low energy consumption with fast enough …
face in sub-micron CMOS technologies. An ultra-low energy consumption with fast enough …
A Systematic Performance Comparison of Ultra Low-Power AES S-Boxes
T Vandenabeele, R Uytterhoeven… - … on Power and …, 2018 - ieeexplore.ieee.org
This paper elaborates on the results of a thorough comparison between different AES S-box
circuits in 28nm Fully Depleted Silicon-On-Insulator (FD-SOI) technology of …
circuits in 28nm Fully Depleted Silicon-On-Insulator (FD-SOI) technology of …
Loadable Kessels Counter
O Benafa, D Sokolov, A Yakovlev - 2018 24th IEEE …, 2018 - ieeexplore.ieee.org
We present the decomposition and implementation of a loadable self-timed counter that can
perform seamless modulo loading and counting operation. The challenges in designing a …
perform seamless modulo loading and counting operation. The challenges in designing a …